AValon Bus Property "maxBurstsize"

[Altera_Forum]

I have to map my custom logic, which is a ddr controller with the Nios Proc via Avalon MM bus interface. So, I was reading Avalon bus specs. I found two similar things which confused me. 

 1.) burstcount : which is a signal type & defines the width of burst count signal. it has a value range 1-11. if we choose value "10" it means we can do 1k transactions in any perticular burst.  the second thing is  2.) maxburstcount : they describe it as "The maximum burst size that a slave can accept". its legal value is 64 & default value is 1.  Can anybody explain the difference b/w them.  thanks in advance...

[Altera_Forum]

burstcount is the actual signal that you will use to tell how many transfers the transaction will contain. you are wrong in saying it defines the width of the burst count signal, that is what maxBurstCount does. maxBurstCount is a constant and is what the maximum value burstcount can contain. 

 So, for example : if maxBurstCount is set to 2, then burstcount will have a width of 2 and can contain the values 1 or 2. if maxBurstCount is set to 4, the burstcount will have a width of 3 and can contain the value 1,2,3,4. I don't think you can have a burstcount of 0, but it is possible i guess.   So in recap:  burstcount is a signal and maxBurstCount is a constant that defines the width of burstcount  Probably not the best definition/explination, but hope this helps.

[Altera_Forum]

*Do not* use a burst count of 0, you'll probably lock up the arbitration logic of whatever slave is being accessed. 

 kbs972 explained the difference quite well. An extra little bit of information:  If you define a burstcount bus of (n-1)..0 the maximum burst value you are allowed to present is 2^(n-1). So for example if I had a burst count signal of 5 bits wide, the maximum value I'm allowed to post is 16 (10000 in binary). In other words the maximum value you can post on the burst count signal is the MSB set to '1' and all other bits set to '0'.  In your example of a burstcount width of 10 that means the maximum burst you can present is 2^(10-1) = 512 beats. I have not seen anything that used a burst count exceeding a max burst count of 128 (burst count width of 8 bits). Also when possible try to match the master and slave burst max burst counts and data widths, this will help avoid burst adapters. Some other useful burst information can be found in here: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf