newbie question on FPGA/CPLD's

[Altera_Forum]

I'm just learning how to program a MAX II device. The device has pins that are meant to be driven by a clock. I assume that that having dedicated clock pins makes implementing timing across logic units much more efficient than using generic signals in the device, but I don't really know what I'm talking about... 

 However, the clock pins have me worried a bit. I assume that if you program them correctly, these devices allow you to program logic units to respond to inputs "instantaneously" and not clock its way through states using an external clock (like the simulators sort of have to do). So that if the external clock is slowed down, I hope that the response of all of the device's logic doesn't slows proportionally...???  So my first questions is:  1) Are the speed of the logic units tied to a clock or, if properly programmed, they behave like regular AND/OR gates that have nano-second scale delay times?  And my 2nd is:  2) What are the typical delay times through the logic units? I'd like to program some logic structures which have "pretty quick" responses to signals, on the order of what you'd get from a dedicated AND/OR gate. Can these FPGA/CPLD's do that?  Sorry for such simple questions, and thanks for any help.  Jason

[Altera_Forum]

To answer the second question first, yes it's ns scale, comparable with e.g. HC or AHC logic. Consult the datasheet or perform a Quartus timing simulation to see the exact logic delays. 

 Clocked logic behaves similar as if built from discrete flip-flop logic devices. As far as the logic response has to travel one ore more flip-flop stages, it will be of course slowed-down with a slower clock. That's usually, what a clocked logic would be expected. You always get exactly the programmed behaviour, also in terms of clock cycles.