NiosII DMA Tutorial

[Altera_Forum]

Hello, may I know where can I get NiosII DMA Tutorial? Currently, I am doing a project to implement DMA on FPGA board. So I would to refer to some tutorials that can help me. Thanks.

[Altera_Forum]

This piece of code sets the bit manually. 

I don't know if there also is a specific function/macro to change the bit.  # include "altera_avalon_dma_regs.h"  int reg; reg = IORD_ALTERA_AVALON_DMA_CONTROL (dma_base_address); IOWR_ALTERA_AVALON_DMA_CONTROL (dma_base_address, reg | ALTERA_AVALON_DMA_CONTROL_RCON_MSK);

[Altera_Forum]

Thanks a lot Cris!! Last question, how can i connect the RD signal that the DMA gives before reading to the FIFO that is outsite my system? I probably have to read it from somewhere. I looked into the embbeded periphals guide from ALTERA but found nothing regarding this RD signal to synchronize with the fifo. 

 If i understood correctly it should happen like that: 1. DMA sends RD signal 2. FIFO gets the RD signal  3. FIFO updated the output data 4. DMA reads from output data  Thanks a lot Cris you are helping me so much!

[Altera_Forum]

You understood correctly. That sequence is correct. 

Anyway I don't know how to make the RD signal available outside the sopc system. You must expose the Avalon PIO read (or select) signal, so I think you probably need a modified version of the pio core. Maybe there's a way to export that signal, but I've never made something alike. You can try this workaround: use a tristate bus with a fake sram component; discard address,wr and rd signals; connect data to your fifo and use cs signal to update fifo output.

[Altera_Forum]

Thanks Cris. I will try that.  

Please take a look at my other thread too ^.^

[Altera_Forum]

--- Quote Start ---  Hi Cris  Long time no see. Thank you for helping me last time. Now I can do data transfer from FIFO to DDR3 via DMA correctly. However, this time I would like to ask your suggestion again.  Currently I'm using three DMAs in my SOPC system to handle three different data transfers from three different FIFOs to a DDR3 memory. I have verified each FIFO and DMA data transfer and all of them work well.   The problem occurs when I put all FIFOs and DMAs in one SOPC system design. I ran the DMA data transfer in sequence (not parallel). Somehow my Nios software hung / stopped. From the Nios software debugging, it was noticed that the Nios software might stop in different location, but mostly it stopped when it tried to open the DMA ('alt_dma_rxchan_open' function) or when it checked the DMA data transfer volatile indicator variable.   Do you have any idea what caused my software hung? Or do you have any suggestion how to figure out the reason behind this problem?  Thanks ... looking forward any replies from you guys!  --- Quote End ---    thank you firstly，i want to ask u about how to do data transfer from FIFO to DDR3 via DMA correctly？