MAX V CFM write/erase fatigue failure mode

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

MAX V CFM write/erase fatigue failure mode

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Hello,

I was wondering if anyone could tell me what the expected failure mode is for a MAX V CPLD that has been programmed beyond the CFM write/erase cycle limit? Will the device simply not verify, or will the device go into an unknown state possibly bricking any connected circuitry?

I'm trying to determine if it is reasonable to expect, in the edge case that a chip has been programmed too many times, that the PCB can simply be reworked to swap out the fatigued component.

Thanks,

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