"FPGA Design Tools" Posts in "Application Acceleration With FPGAs"

Top Taggers

User

Count

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Terms of Use
*Trademarks
Cookies
Privacy
Supply Chain Transparency
Site Map

Error when I run vector-add example on FPGA OpenCL. ERROR: Unable to find Intel(R) FPGA OpenCL platform. by anaza3 Novice in Application Acceleration With FPGAs 08-03-2020 0 3	0	3
Shift register implementation by ADua0 Beginner in Application Acceleration With FPGAs 01-09-2020 0 1	0	1
Can't run DSE II on a high performance computer. by SAbde7 Beginner in Application Acceleration With FPGAs 11-19-2019 0 9	0	9
How can I use a specific compilation/exploration point from DSEII for my actual project? by SAbde7 Beginner in Application Acceleration With FPGAs 11-07-2019 0 12	0	12
What are seeds? by SAbde7 Beginner in Application Acceleration With FPGAs 09-12-2019 0 1	0	1
Dsp utilization for arithmetic operations by ADua0 Beginner in Application Acceleration With FPGAs 09-05-2019 0 2	0	2
Intel Opencl memory issue by ADua0 Beginner in Application Acceleration With FPGAs 09-04-2019 0 1	0	1
Intel opencl kernel execution by ADua0 Beginner in Application Acceleration With FPGAs 08-24-2019 0 5	0	5
How do I use the Avalon MM slave template to connect a PCIE DMA to FIFOs inside my custom logic? by SAbde7 Beginner in Application Acceleration With FPGAs 08-14-2019 0 3	0	3
Intel opencl Fpga kernel after compilation by ADua0 Beginner in Application Acceleration With FPGAs 08-06-2019 0 10	0	10
How to create an Avalon Memory Maped FIFO with different input and output data widths in the Platform designer? by SAbde7 Beginner in Application Acceleration With FPGAs 07-30-2019 0 1	0	1
Intel opencl post routing analysis by ADua0 Beginner in Application Acceleration With FPGAs 07-28-2019 0 1	0	1
Intel Opencl kernel compiling time by ADua0 Beginner in Application Acceleration With FPGAs 06-27-2019 0 7	0	7
Intel opencl report by ADua0 Beginner in Application Acceleration With FPGAs 06-19-2019 0 3	0	3
Synchronization issues on Implementation of Buffer Management for OpenCL Kernels by MAstr Novice in Application Acceleration With FPGAs 05-29-2019 1 4	1	4
Double buffering by ADua0 Beginner in Application Acceleration With FPGAs 05-27-2019 0 2	0	2
Intel Opencl FPGA channels by ADua0 Beginner in Application Acceleration With FPGAs 05-23-2019 0 7	0	7
FPGA Code Customization for the DLA by SBioo Beginner in Application Acceleration With FPGAs 05-13-2019 0 2	0	2
Register implementation in OpenCL by ADua0 Beginner in Application Acceleration With FPGAs 05-03-2019 0 1	0	1
Intel opencl Dynamic profiler report by ADua0 Beginner in Application Acceleration With FPGAs 04-20-2019 0 19	0	19
Separate queue synchronization and buffer data corruption on Feed-Forward Design Model with Buffer Management by MAstr Novice in Application Acceleration With FPGAs 04-09-2019 1 1	1	1
Host-to-Intel arria streaming over PCIe by SBioo Beginner in Application Acceleration With FPGAs 04-01-2019 0 8	0	8
Issue with Dynamic profiling for Autorun kernels. by MFaiz Beginner in Application Acceleration With FPGAs 12-12-2018 0 5	0	5
Design Example for Autorun kernel by MFaiz Beginner in Application Acceleration With FPGAs 12-05-2018 0 2	0	2
OpenVINO - "Error: Failure due to generic standard exception" when running inference on FPGA by CJian1 Beginner in Application Acceleration With FPGAs 08-01-2018 0 0	0	0