Tag: "Fpgas"

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Arria 10 External Memory Interface Invalid Data Width by Altera_Forum Honored Contributor II in FPGA Intellectual Property 06-04-2024 0 4	0	4
What is the availability of the Altera Direct RF-Series FPGAs? by digitalone Beginner in Programmable Devices 03-25-2024 0 7	0	7
Intel MAX 10 on-chip Flash Memory IP core by nyquist0102 Beginner in Intel® Quartus® Prime Software 03-03-2024 0 3	0	3
Getting started with bare-metal application development with the Cyclone V by Altera_Forum Honored Contributor II in Programmable Devices 01-28-2024 0 14	0	14
Arria 10 PCIe Avalon-MM DMA Reference Design: Read/Write Timeout by Altera_Forum Honored Contributor II in FPGA Intellectual Property 11-07-2023 0 7	0	7
DSP Builder Advanced: integrator and differentiator blocks by Altera_Forum Honored Contributor II in FPGA Intellectual Property 05-25-2023 0 1	0	1
Why is Altera® USB Blaster not detected by Quartus® Programmer when it is recognized correctly in Device Manager? by NMadh Beginner in Intel® Quartus® Prime Software 10-27-2022 0 2	0	2
Intel® FPGA Announcements Deliver Programmable Innovation with a Customer Focused Strategy by Deepali_Trehan Employee in FPGA 09-26-2022 0 0	0	0
Need more infomation about intel MAP accelerator card by LilySpark Novice in Programmable Devices 09-01-2022 0 7	0	7
Cost-optimized FPGAs by _sirius_ Beginner in FPGA Intellectual Property 08-19-2022 0 1	0	1
A Guide to AI Partner and Accelerator Programs for Startups by Jack_Erickson Employee in Artificial Intelligence (AI) 08-18-2022 1 0	1	0
Cannot program terasIC DE-10 Nano Kit with Quartus Prime Lite (18.0) on Linux (Ubuntu 17.10) by CHend1 Beginner in Intel® Quartus® Prime Software 03-03-2022 0 4	0	4
Quartus 19.1 Standard on Windows and Stratix IV Hard Pci-Express missing file by ltazz1 Beginner in FPGA Intellectual Property 01-20-2022 0 12	0	12
Quartus fitter license fails on the 5CSEMA5F31C6 Cyclone V for a Terasic DE1-SoC Board by SEdwa8 Beginner in Intel® FPGA Software Installation & Licensing 11-03-2021 0 2	0	2
Cyclone V GT Avalon-MM DMA Reference Design Read/Write Timeout by Altera_Forum Honored Contributor II in FPGA Intellectual Property 07-23-2021 0 2	0	2
Flash Loader IP not loaded on device 1? by FN0001 Beginner in FPGA, SoC, And CPLD Boards And Kits 07-19-2021 0 7	0	7
digital simulation model for Altera SoC (Arria 10) by Altera_Forum Honored Contributor II in Programmable Devices 05-25-2021 0 3	0	3
Interrupt handling problem using linux with DE1_SoC cyclone V by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 05-12-2021 0 1	0	1
Setting up TrustZone on Cyclone V FPGA board by ADavi10 Beginner in Nios® V/II Embedded Design Suite (EDS) 04-30-2021 0 2	0	2
IOPLL Source Synchronous Compensation Issue? -- Arria 10 by Altera_Forum Honored Contributor II in Programmable Devices 04-19-2021 0 6	0	6
Is there an example design available for doing an RSU across a UART discrete (without the use of a Nios II)? My target is the MAX10 but that isn't as critical. I would prefer VHDL over Verilog, but I will take what I can get. by Falkster Beginner in Programmable Devices 03-16-2021 0 3	0	3
arria 10 interoperability reference design is not work..! by Altera_Forum Honored Contributor II in FPGA, SoC, And CPLD Boards And Kits 03-04-2021 0 3	0	3
Which programming file format should be used for partial programming of serial flash with remote update feature? by PJancso Beginner in FPGA Intellectual Property 02-23-2021 0 2	0	2
Avalon streaming interface in HLS component can't connect to streams in streaming_dma_afu example. by RBash Novice in Programmable Devices 01-25-2021 0 5	0	5
Arria II IBIS model by ppp777 Beginner in Programmable Devices 12-21-2020 0 1	0	1