	Error(18694) with LVDS SERDES IP by J314 Beginner in FPGA Intellectual Property 01-26-2023 0 2	0	2
	Cyclone V transceiver status rx_disperr and rx_errdetect inactive, even when unplugging SMA cable by JC_FPGA Novice in FPGA Intellectual Property 06-28-2021 0 2	0	2
	LVDS SERDES IP with cascaded downstream PLL by MichaelB New Contributor I in FPGA Intellectual Property 10-19-2020 0 3	0	3

"SERDES" Posts in "FPGA Intellectual Property"