Tag: "Stratix"

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How can I know what modulation type use in BER measure by DeadEnd New Contributor I in Intel® Quartus® Prime Software 05-22-2024 0 2	0	2
Question Regarding Clock Synchronization in EyeQ BER function by DeadEnd New Contributor I in Intel® Quartus® Prime Software 05-15-2024 0 7	0	7
Stratix 10 MCDMA host: Queue reset failed by Arnab1 Novice in Programmable Devices 05-08-2024 0 6	0	6
Questions about BER Data Rate. by DeadEnd New Contributor I in Intel® Quartus® Prime Software 03-12-2024 0 3	0	3
E-Tile Ethernet Hard IP MAC address by TheEngineer7 Beginner in Programmable Devices 02-29-2024 0 1	0	1
New compiler (2024.0) breaks FPGA compilation and execution in devcloud by rochextopher Beginner in Intel® DevCloud 02-12-2024 0 4	0	4
Firmware for Intel FPGA PAC by BLB Beginner in Application Acceleration With FPGAs 06-22-2023 0 2	0	2
DDR4 calibration in Stratix 10 1SG040HH3F35E2LG device by David_S1 Beginner in Programmable Devices 05-15-2023 0 3	0	3
stratix 10 FPGA manager to load FPGA config from Ateml by RAJU_CN Beginner in Programmable Devices 03-25-2023 0 3	0	3
Active serial configuration by MCipr5 Novice in Programmable Devices 03-23-2023 0 8	0	8
DevCloud: Cannot compile Stratix 10 kernel (Tcl error) by Mdcc_UVa New Contributor I in Intel® High Level Design 01-25-2023 0 18	0	18
Stratix 10 BTS. Connection Lost. Quartus 18.0 Pro & Win10 by covfefe New Contributor I in FPGA, SoC, And CPLD Boards And Kits 01-16-2023 0 6	0	6
Application Engineer. Stratix GX EPISGX10D upgrade support wanted. by John_Whitcraft_Comp_E Novice in Programmable Devices 12-06-2022 0 7	0	7
Connection of Stratix 10 GX FPGA Development Kit by jamesjjc Novice in FPGA, SoC, And CPLD Boards And Kits 11-03-2022 0 9	0	9
Stratix V PCIe CvP not working by Petkov_Alex New Contributor I in FPGA, SoC, And CPLD Boards And Kits 09-26-2022 0 15	0	15
Intel Delivers a Game-Changing, Analog-Enabled Direct RF FPGA Portfolio by John_Sotir Employee in FPGA 09-26-2022 0 0	0	0
dense packing for fourteennm_mlab_cell and not related register by matota1 Beginner in Programmable Devices 09-05-2022 1 4	1	4
The Growing Need for Scalable Solutions in the Emulation and Prototyping of Complex Designs by Jatinder_Singh Employee in FPGA 06-29-2022 0 0	0	0
Intel Stratix 10 GX Ethernet Hard IP by AK-1 Novice in Programmable Devices 06-08-2022 0 11	0	11
Stratix 10 : Critical Warning: DDR Timing requirements not met by Renardo18 New Contributor I in FPGA Intellectual Property 05-25-2022 0 8	0	8
Silicom Showcases FPGA SmartNIC Acceleration Cards for O-RAN Apps at MWC Barcelona 2022 by Sabrina_Gomez Employee in FPGA 02-24-2022 0 0	0	0
Design files for Application Note AN367 by msebb Novice in Programmable Devices 01-24-2022 0 3	0	3
Design files for Application note AN454 by msebb Novice in Programmable Devices 01-24-2022 0 2	0	2
Stratix 10 UCID IP bug: partition conflict by roeekalinsky Valued Contributor I in FPGA Intellectual Property 01-19-2022 0 13	0	13
Design files for Application Note AN367 by msebb Novice in Programmable Devices 01-17-2022 0 0	0	0