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fxu001
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About fxu001
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Posted
count missing cell that cause Questa error out
on
FPGA Intellectual Property
.
07-06-2020
10:34 AM
Got a Kudo for
Re: How to solve error message for 17044 using device Arria 10: 10AX027H434i3SG in Quartus 18.1. It is urgent issue!
.
06-23-2020
01:23 AM
Posted
Re: How to solve (38): in protected region?
on
FPGA Intellectual Property
.
03-06-2020
06:10 PM
Posted
How to solve (38): in protected region?
on
FPGA Intellectual Property
.
02-11-2020
10:04 PM
Posted
Re: click IP but can't launch the gui in Quartus 14.0
on
FPGA Intellectual Property
.
10-22-2019
04:51 PM
Posted
Re: click IP but can't launch the gui in Quartus 14.0
on
FPGA Intellectual Property
.
10-21-2019
09:57 PM
Posted
Re: click IP but can't launch the gui in Quartus 14.0
on
FPGA Intellectual Property
.
10-18-2019
11:14 PM
Posted
Re: click IP but can't launch the gui in Quartus 14.0
on
FPGA Intellectual Property
.
10-18-2019
10:20 PM
Posted
click IP but can't launch the gui in Quartus 14.0
on
FPGA Intellectual Property
.
10-18-2019
12:11 AM
Posted
Re: How to interpret 8b/10b convert in the JESD204b bus
on
FPGA Intellectual Property
.
10-04-2019
09:16 PM
Posted
Re: How to program phy device
on
FPGA Intellectual Property
.
09-20-2019
05:31 PM
Posted
How to program phy device
on
FPGA Intellectual Property
.
09-18-2019
09:51 PM
Posted
Re: How to interpret 8b/10b convert in the JESD204b bus
on
FPGA Intellectual Property
.
08-14-2019
04:25 PM
Posted
Re: How to interpret 8b/10b convert in the JESD204b bus
on
FPGA Intellectual Property
.
08-01-2019
05:12 PM
Posted
Re: measure the length in the SignalTap in Quartus 18.1
on
Application Acceleration With FPGAs
.
08-01-2019
04:59 PM
Posted
Re: what condition to get JESD204B serial output pin toggling? (it is urgent)
on
FPGA Intellectual Property
.
07-30-2019
05:15 PM
Posted
Re: timing in I/O pads
on
FPGA, SoC, And CPLD Boards And Kits
.
07-25-2019
05:06 PM
Posted
Re: timing in I/O pads
on
FPGA, SoC, And CPLD Boards And Kits
.
07-25-2019
04:17 PM
Posted
measure the length in the SignalTap in Quartus 18.1
on
Application Acceleration With FPGAs
.
07-23-2019
01:25 AM
Posted
Re: timing in I/O pads
on
FPGA, SoC, And CPLD Boards And Kits
.
07-17-2019
04:43 PM
Latest posts by fxu001
Subject
Views
Posted
count missing cell that cause Questa error out
FPGA Intellectual Property
72
07-06-2020
10:34 AM
Re: How to solve (38): in protected region?
FPGA Intellectual Property
61
03-06-2020
06:10 PM
How to solve (38): in protected region?
FPGA Intellectual Property
169
02-11-2020
10:04 PM
Re: click IP but can't launch the gui in Quartus 14.0
FPGA Intellectual Property
54
10-22-2019
04:51 PM
Re: click IP but can't launch the gui in Quartus 14.0
FPGA Intellectual Property
54
10-21-2019
09:57 PM
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Community Statistics
Posts
47
Solutions
0
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0
Kudos received
1
Member Since
03-25-2019
