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For the latest information on Intel’s response to the Log4j/Log4Shell vulnerability, please see Intel-SA-00646
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Dr. Rafael Asenjo, Professor of Computer Architecture at the University of Malaga, Spain, obtained a PhD in Telecommunication Engineering in 1997 and was an Associate Professor at the Computer Architecture Department from 2001 to 2017. His research interests include programming models, parallel programming, heterogeneous computing, parallelization of irregular codes and energy consumption. He has been using the Intel TBB library since 2008 and over the last five years, he has focused on productively exploiting heterogeneous chips leveraging TBB as the orchestrating framework. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to research into CPU+FPGA chips while visiting U. of Bristol. He has co-authored the latest book on TBB (Pro TBB, Apress, 2019).
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Member Since ‎12-17-2007