Branching, instruction-miss and prefetcher event counters

[T_C]

Hi, would somebody be able to tell me which event counters I should add to a custom analysis for the following:

1) How successful the prefetcher is

2) L1 Instruction cache misses

3) Pipeline stalls regardless of cause

4) Direct Branch mispredictions

5) Indirect Branch mispredictions

Also, what is the difference between event names with and without the _PS, like:

BR_MISP_RETIRED.ALL_BRANCHES

BR_MISP_RETIRED.ALL_BRANCHES_PS

Thank you in advance,

[David_A_Intel1]

Hi T C:

"PS" means precise.  It has to do with when the instruction pointer is captured after the event counter triggers the interrupt.

We can't just "tell you" which events to use.  First, it depends entirely on which processor you are collecting the data on.  Second, some processors may or may not support some of the metrics you are looking for.  The best bet is to see the tuning guides at http://www.intel.com/vtune-tuning-guides.  These guides are specific to each generation of microarchitecture and show what metrics are available, accurate, and useful in analyzing performance efficiency.

[T_C]

MrAnderson (Intel) wrote:

Hi T C:

"PS" means precise.  It has to do with when the instruction pointer is captured after the event counter triggers the interrupt.

We can't just "tell you" which events to use.  First, it depends entirely on which processor you are collecting the data on.  Second, some processors may or may not support some of the metrics you are looking for.  The best bet is to see the tuning guides at http://www.intel.com/vtune-tuning-guides.  These guides are specific to each generation of microarchitecture and show what metrics are available, accurate, and useful in analyzing performance efficiency.

Hi, thank you for the explanation and guide. I am using Ivy Bridge (not Xeon), downloaded the guide but it doesn't specifically mention measuring the prefetcher rate?

Regarding "PS" - if there is a PS and non-PS version available, should the PS one always be preferred?

Thanks,

[Bernard]

>>>3) Pipeline stalls regardless of cause>>> You can split Pipeline stalls analysis into Front-End and Back-End stalls.