Community
cancel
Showing results for 
Search instead for 
Did you mean: 
psing51
Beginner
420 Views

DRAM Bandwidth Bound vs Memory Bandwidth Bound

Hi,
I am trying parallel studio 2020u1 on rhel 7.6 for an application. I tried HPC performance analysis, memory bandwidth analysis and microarchtecture analysis on an application.

Here are the values of 2 metrics which i wish to understand more -

hpc performance/memory bandwidth analysis -
Memory Bound > DRAM Bound > DRAM Bandwidth Bound = 76.7%

microarchitecture analysis -
Back-End Bound > Memory Bound > DRAM Bound > Memory Bandwidth = 42.7%

Is this interpretation correct - "If execution time was say 100 seconds, and 90Gbps and above is treated as high memory bandwidth utilization then can i say that for 76 seconds the application used high DRAM bandwidth and, 42% of the total clockticks issued during application execution waited to get data from memory."

For memory Bound metric  (L1,L2,L3,DRAM Bound) I understand that lower value indicates better L3 Utilization.
 2.6% of clockticks were L3 Bound in this case.. This means that the 2.3% of the clockticks were wasted while retreiving data from L3 cache? As far as i understand, if CPU is unable to find data in cache then DRAM Memory is searched for data/instruction. So If Stall for DRAM/Memory is 42.7% clockticks then i was expecting almost similar/higher value for L3 Bound instructions.






0 Kudos
3 Replies
JananiC_Intel
Moderator
369 Views

Hi Puneet,

Thanks for reaching out.

We are forwarding the case to SME.


97 Views

Hi Puneet,


The "DRAM Bandwidth Bound" metric represents percentage of elapsed time the system spent with high DRAM bandwidth utilization. While, the "Memory Bandwidth" metric represents fraction of cycles during which an application could be stalled due to bandwidth limits of DRAM. Therefore, in the example you quoted, your interpretation is correct.


L3 bound metric shows how often CPU was stalled on L3 cache, while DRAM bound metric shows how often CPU was stalled on DRAM, as a result both metrics need not follow each other even though L1 -> L2 -> L3 -> DRAM is the memory hierarchy.


Please let me know if you have further questions.


Best regards,

Amar




49 Views

Hi Puneet,


Closing this thread due to inactivity. We will no longer respond to this thread. If you require additional assistance from Intel, please start a new thread. Any further interaction in this thread will be considered community only.


Best regards,

Amar


Reply