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Hi!
I use VTune to profile an application running on the Intel Itanium platform. I want to see how the cache hierarchy performs:
Strangely, I don't get any samples for the event L3_READS-DATA_READ.ALL. It's strange, because I experience a lot of L2 cache data misses, so these misses should go directly to the L3 cache in my opinion. Hence, I can't believe what vTune reports right now.
It's a very special question, so are there Itanium experts who know why vTune reports there are not L3 cache data read events? The machine I use has 2 Itanium Montecitos, with 2 x 6MB unified L3 cache each.
If you need more information, let me know.
Thanks so much in advance!
Andreas
I use VTune to profile an application running on the Intel Itanium platform. I want to see how the cache hierarchy performs:
Strangely, I don't get any samples for the event L3_READS-DATA_READ.ALL. It's strange, because I experience a lot of L2 cache data misses, so these misses should go directly to the L3 cache in my opinion. Hence, I can't believe what vTune reports right now.
It's a very special question, so are there Itanium experts who know why vTune reports there are not L3 cache data read events? The machine I use has 2 Itanium Montecitos, with 2 x 6MB unified L3 cache each.
If you need more information, let me know.
Thanks so much in advance!
Andreas
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Quoting - defender1234
Hi!
I use VTune to profile an application running on the Intel Itanium platform. I want to see how the cache hierarchy performs:
Strangely, I don't get any samples for the event L3_READS-DATA_READ.ALL. It's strange, because I experience a lot of L2 cache data misses, so these misses should go directly to the L3 cache in my opinion. Hence, I can't believe what vTune reports right now.
It's a very special question, so are there Itanium experts who know why vTune reports there are not L3 cache data read events? The machine I use has 2 Itanium Montecitos, with 2 x 6MB unified L3 cache each.
If you need more information, let me know.
Thanks so much in advance!
Andreas
I use VTune to profile an application running on the Intel Itanium platform. I want to see how the cache hierarchy performs:
Strangely, I don't get any samples for the event L3_READS-DATA_READ.ALL. It's strange, because I experience a lot of L2 cache data misses, so these misses should go directly to the L3 cache in my opinion. Hence, I can't believe what vTune reports right now.
It's a very special question, so are there Itanium experts who know why vTune reports there are not L3 cache data read events? The machine I use has 2 Itanium Montecitos, with 2 x 6MB unified L3 cache each.
If you need more information, let me know.
Thanks so much in advance!
Andreas
Hi Andreas,
I think that you may check:
1. If your application has many memory accesses, and there are many L2D_MISSES. Since L2D cache misses happened, the request will be sent to L3 for cache read.
2. Simplywrite codeto read arrays in a long loop, like as c =a + b;"i" could be 0 to 6,000,000, array data type as double. I believe thatVTune Analyzer can capturesamples for eventL3_READS-DATA_READ.ALL
3. Sometimes samples for L3_* events are not shown - it doesn't mean this event didn't occur, go "Sampling Configure" to change "Sample After Value" (SAV) to smaller. Sampling collector will capture samples.
Regards, Peter
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