Level 2 data cache event counters?

[T_C]

Below is a list of all the event counter I have available on my Ivy Bridge CPU. It contains "L1D" cache event counters, but there are no "L2D" counters- only "L2". I was under the impression the L2 cache is split in to data and instruction caches. 

(I have read the descriptions of the below event counters and the "L1D" says "L1 data cache" and the "L2" says "L2 cache", implying it is not specific to the data cache).

What event counters should I use to measure data cache misses for L1/L2/L3, ignoring instruction cache misses?

ARITH.FPU_DIV_ACTIVE

BACLEARS.ANY

BR_MISP_RETIRED.ALL_BRANCHES_PS

CPU_CLK_UNHALTED.REF_TSC

CPU_CLK_UNHALTED.THREAD

CYCLE_ACTIVITY.CYCLES_NO_EXECUTE

CYCLE_ACTIVITY.STALLS_L1D_PENDING

CYCLE_ACTIVITY.STALLS_L2_PENDING

CYCLE_ACTIVITY.STALLS_LDM_PENDING

DSB2MITE_SWITCHES.PENALTY_CYCLES

DTLB_LOAD_MISSES.STLB_HIT

DTLB_LOAD_MISSES.WALK_DURATION

DTLB_STORE_MISSES.STLB_HIT

DTLB_STORE_MISSES.WALK_DURATION

ICACHE.IFETCH_STALL

ICACHE.MISSES

IDQ.ALL_DSB_CYCLES_4_UOPS

IDQ.ALL_DSB_CYCLES_ANY_UOPS

IDQ.ALL_MITE_CYCLES_4_UOPS

IDQ.ALL_MITE_CYCLES_ANY_UOPS

IDQ.MS_CYCLES

IDQ.MS_UOPS

IDQ_UOPS_NOT_DELIVERED.CORE

IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE

ILD_STALL.LCP

INST_RETIRED.ANY

INST_RETIRED.PREC_DIST

INT_MISC.RECOVERY_CYCLES

ITLB_MISSES.WALK_DURATION

L1D.REPLACEMENT

L1D_PEND_MISS.PENDING

L2_LINES_IN.ALL

LD_BLOCKS.NO_SR

LD_BLOCKS.STORE_FORWARD

LD_BLOCKS_PARTIAL.ADDRESS_ALIAS

MACHINE_CLEARS.COUNT

MACHINE_CLEARS.MASKMOV

MACHINE_CLEARS.MEMORY_ORDERING

MACHINE_CLEARS.SMC

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS

MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM

MEM_LOAD_UOPS_RETIRED.L1_MISS

MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS

MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS

MEM_UOPS_RETIRED.ALL_STORES_PS

MEM_UOPS_RETIRED.SPLIT_LOADS_PS

MEM_UOPS_RETIRED.SPLIT_STORES_PS

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM_0

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_0

RESOURCE_STALLS.SB

RS_EVENTS.EMPTY_CYCLES

RS_EVENTS.EMPTY_END

UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC

UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC

UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC

UOPS_ISSUED.ANY

UOPS_RETIRED.RETIRE_SLOTS

[T_C]

T C wrote:

Below is a list of all the event counter I have available on my Ivy Bridge CPU. It contains "L1D" cache event counters, but there are no "L2D" counters- only "L2". I was under the impression the L2 cache is split in to data and instruction caches. 

(I have read the descriptions of the below event counters and the "L1D" says "L1 data cache" and the "L2" says "L2 cache", implying it is not specific to the data cache).

What event counters should I use to measure data cache misses for L1/L2/L3, ignoring instruction cache misses? 

Have attached the list of hardware event counters in this message.

[David_A_Intel1]

T C:

please check out this thread: http://software.intel.com/en-us/forums/topic/506796 

yes, L2 cache is "unified" wrt the CPU.  Are you doing any GPU code excution?