I am new to this form so I am not quite sure if this is the place for this question, but as seeing VTune probably does something similar, I thought it was worth a shot.
I am interested in generating L3 address trace in a nehalem i7 core (or even better a DRAM memory trace) for a running application. I was thinking that it may be possible to take an exception whenever an L2 miss event occurs and to read the appropriate register of the address that fails and save it to a buffer. Is there any support to do something like this that someone knows about? At the very least, I would like to know if the i7 supports taking an exception on a performance event like the L2 miss count being incremented.
Thanks in advance,
This is exactly what the VTune analyzer does to collect sampling data. However, I am not prepared, or able, to tell you how to build your own app to do that. (Note: it does not take an exception EVERY time an L2 miss occurs - that's a good way to hang your system! ;-)
Please check around these forums (i.e., other forums). I know that a similar question came up recently and was moved to the appropriate forum. You may find help there.