Sandybridge Data L1 load/store access and DATA L3 load/store Misses

[Ahmad]

I have sandybridge machine and I am using the following counters to measure L1 load/store accesses, L1 misses, L3 misses and DTLB misses through VTUNE_XE_2013. I am not sure if I am using the correct counters for L1 access and L3 Misses. Please let me know if the following performance counters are correct:

L1 load accesses: MEM_UOPS_RETIRED.ALL_LOADS_PS

L1 store accesses: MEM_UOPS_RETIRED.ALL_STORES_PS

L3 Misses: MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS

DTLB Misses: DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK + DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

Thanks.

[David_A_Intel1]

Please see our processor tuning guides at http://www.intel.com/vtune-tuning-guides. 

(Sorry, originally I specified the wrong protocol, https instead of http. :(  Fixed now.)