Agilex 5 Precision DSP block simulations

[S_J_S]

Hi,

I'm using the Precision DSP blocks in my Agilex 5 design; i have a floating point Add (FP_Add_native_DSP) and a floating point MAC (FP_MAC_native_DSP), but when i try and run simulations with these in place i'm seeing odd behavior:

1/ The adder is not doing an addition, the output is merely following one of the input pins.

2/ The MAC is giving an output but this does not match the output i'm seeing from a similar MAC targeted for the Arria 10 FPGA. The Arria 10 design is proven on silicon so i would have thought the simulation model for this is correct.

The above is making me nervous and i'm seeking clarification that:

1/ There are indeed bugs in the simulations models - if so is there a patch available?

2/ The Floating Point DSP functions work correctly on the actual Agilex 5 silicon.

I look forward to hearing from you.

Simon

[CheePin_C_Intel]

Hi Simon,

Thank you for filing this case and sharing the details. As I understand it, you have some inquiries related to the Agilex 5 DSP. Please allow me some time to review the information, and I’ll get back to you as soon as possible.

[CheePin_C_Intel]

Hi Simon,

Would you be able to share simple simulation examples that replicates the behavior you observed? This would greatly help in my debugging efforts.

If possible, it would also be beneficial to have a reference simulation that passes on Arria 10, so I can use it for comparison and analysis.

Thank you in advance for your support.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

Just would like to follow up with you on this. Please let me know if there is any concern. Thank you.

[S_J_S]

Hi,

To replicate the behavior with the Adder, simply create a wrapper around it and try and Add two number together - you'll see the simulation fails and the output simply tracks one of the inputs.

It's a bit more involved with the MAC, although if you run a simulation with it doing multiple MAC and then de-assert the accumulate signal every 5 cycles you'll notice the outputs do not match what you'd expect. By that i mean they do not match what i get from Python or from running the same testbench on hardware.

It's tricky getting test cases to you at this time as i don't have the spare time required to put something together and package it all up etc. Do you know of nay issues with the simulation models? Are there any later versions available ?

Many thanks,

Simon

[S_J_S]

By the way; is it worth me posting this question in other categories? I find the listed categories do not really match what my question relates to so it's hard to know if this is the correct one.

[CheePin_C_Intel]

Hi,

Sorry for the delay. Please allow me additional time to create test cases to replicate your observation. Please ping if you do not hear back from me by mid of the week. Thank you.

[CheePin_C_Intel]

Hi,

Since you're currently unable to provide a simulation test case, I’ve created a simple test using the fp32_add function from the Native Floating Point DSP IP for Intel Agilex FPGA. The simulation was performed using Quartus 24.3 targeting an Agilex 5 device, and it appears to run successfully, as shown in the attached screenshot.

I’ve shared the simulation folder (fp_add_dsp.zip) via email for your reference. You can review the following files to rebuild the simulation on your end:

/sim/mentor/msim_setup.tcl
/sim/fp_add_dsp.v
tb_fp_add_dsp.v

Please let me know if you have any questions or need further assistance. Thank you.

[CheePin_C_Intel]

Hi,

Just to keep you informed — I’ve tested the Native Floating Point DSP IP in MAC mode, and the simulation appears to run correctly (please ignore the last 3 signals which are irrelevant).

Given the discrepancies in our observations, please feel free to share your simulation files that replicate the issue you're seeing. This will help me investigate further and identify any potential differences or root causes.

Let me know if you have any questions or need additional support. Thank you.

Best regards,
Chee Pin

[S_J_S · Accepted solution]

Hi,

Thank you for looking into this further.

I agree the Adder is correct and i've also now seen correct behavior, so i'm not sure why it appeared incorrect previously.

Regarding the MAC; i still see an issue and there has now been an IPS case opened for it (via our AE).

Since there is an IPS case open i'm happy to mark this particular query as closed.

Thank you again for your support,

Simon

[CheePin_C_Intel]

Hi Simon,

Thanks for your update. I believe that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much