Agilex FPGA Quartus project simulation issue

[BXia]

To whom it may concern,

我们在仿真基于Agilex FPGA的工程时，发现mac的link比别的开发板（基于Stratix 10 FPGA）慢了很多，agilex的mac大概需要48wns才能link上，而Stratix 10 FPGA的mac大概只需要15wns就能link上。

我们分析的原因是，agilex生成的ip core（phy_10g_etile）里phy的ready信号拉起的慢，导致收发端mac的link也相应的推迟。请问，有没有加速仿真的方式，能将link的时间提前到10多wns就能完成。

谢谢。

(Description in English)

I am using Agilex B2E2 FPGA board (DE10-Agilex from Terasic), and built a Quartus project which included phy_10g_etile MAC IP core, I simulated the project and found the MAC was finally linked after about 48wns. A screenshot is attached here for your reference.

I used Stratix 10 FPGA board (DE10-Pro from Terasic too) before, the MAC can be linked in about 15wns.

Could you help analysing what maybe happened for my Agilex project?  How to accelerate the time that MAC link while simulating?

Thanks in advance.

[paveetirrasrie_Intel]

Hi Xia,

It is possible that different device might have different linking timing. It may due to various IP setting.

Please give me sometime to investigate this and will get back to you with updates.

Regards,

Pavee

[paveetirrasrie_Intel]

Hi,

Apologize for the delay. It may due to different IP setting or device. I'm lasing with my teammates on this. Will update you on this soon

Regards,

Pavee

[paveetirrasrie_Intel]

Hi,

After having discussion with my teammates, looks like there will be different in simulation model in different devices.

So I don't think there's any specific way to shorten the timing for linking as it depends on simulation models.

Regards,

Pavee

[paveetirrasrie_Intel]

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