To whom it may concern,
(Description in English)
I am using Agilex B2E2 FPGA board (DE10-Agilex from Terasic), and built a Quartus project which included phy_10g_etile MAC IP core, I simulated the project and found the MAC was finally linked after about 48wns. A screenshot is attached here for your reference.
I used Stratix 10 FPGA board (DE10-Pro from Terasic too) before, the MAC can be linked in about 15wns.
Could you help analysing what maybe happened for my Agilex project? How to accelerate the time that MAC link while simulating?
Thanks in advance.
It is possible that different device might have different linking timing. It may due to various IP setting.
Please give me sometime to investigate this and will get back to you with updates.
After having discussion with my teammates, looks like there will be different in simulation model in different devices.
So I don't think there's any specific way to shorten the timing for linking as it depends on simulation models.
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