Develop a complete RESNET33 model on Fpga using Vhdl.

[RKhaz]

Hello,

I am working on the ZYNQ Fpga, my task is to develop a complete RESNET33 model on Fpga using Vhdl. I will not be training the model but using the pre-trained weights, hence I will be doing only the inference part. 

So far I have developed a single layer of CNN(Zero-padding, Convolution, ReLu, Bias, MaxPool). I need some insights from you, am I heading in the right direction?

Is it possible to implement on Vhdl or should i chang approach to a more easy way?

Please note: Input Image is a grayscale bit stream.

[HRZ]

Even though your question is not FPGA-dependant, ZYNQ FPGAs are made by Xilinx and not Intel; hence, it is probably best to ask for help on Xilinx's forums.

[JEYANTHKRI_N_Intel]

Hi,

Thanks for reaching out to us.

 As this forum is focussed on Intel AI related questions and since you are working on the ZYNQ Fpga which is made by Xilinx and not Intel, we recommend you to post the question in Xilinx's forum.

[RKhaz]

Hello HRZ and Jeyanth,

Yes you are right, Thank you.

[JEYANTHKRI_N_Intel]

Hi ,

Glad to hear that the solution provided helped

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