Traditional altera FPGA design flow supports opencore plus feature,which enable customer to generate a time limited .sof to download into FPGA to evaluate performance before placing IP core order.
I was wondering if OPAE design flow also supports opnecore plus feature and allow customer to generate a similar restricted image to download into FPGA for evaluation purpose before placing IP order.
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qs-ias-v1-2.pdf in page 5 stated: "The Acceleration Stack supports creation of AFU images with either RTL or OpenCL* design flows. An AFU image includes the AFU PR region bitstream and metadata that provides OPAE information on AFU characteristics and operational parameters. The current release supports dynamically swapping a single AFU image in a single PR region per installed Intel PAC. "
For you information, the opencore plus is IP related to Quartus and you may need the Quartus to compile the design. Hence, you will need the Quartus license for this progress.
Thanks for your feedback.
Based on your feedback, a customer , whose design included a non free INTEL IP core in AFU following the OPAE design flow, can not generate a restrict image file for hardware evaluation purpose,.
This is a back-forward step comparing to traditional FPGA design flow, which supports running IP first before buying it.
your feedback is still very useful and valuable.
have a good day.