It seems that Intel FPGA's "Programming Guide" does not say there is a maximum capacity for the channel size (FIFO buffer). It just says "__attribute__((depth(N))" can be used to define a depth channel. But in their examples, the N is quite small (say 10).
So can the channel still be used if I want to transfer large amount of data (e.g., a large buffer that stores a large 2D or 3D matrix) between two kernels? Using global memory (DDR) is low efficient. If the channel does have some capacity limit, is there any way to use it?
Thanks in advance!
Channels are implemented using register and Block RAMs on the FPGA. The maximum channel size is limited by the amount of such resources available on your FPGA. This is essentially in the order of a few Megabytes. You should not use channels for storing data; they are made for streaming data from one kernel to another.