Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
493 Discussions

FPGA Agelix F-tile

TabetS
Beginner
‎03-06-2023 05:42 PM
566 Views

#**Error: (vsim-3043) Unresolved reference to 'eth_f_hw' in eth_f_hw.IP_INST[0.hw_ip_ top.dut.eth_f_0.sip_inst.rx_lane_desired_state.

0 Kudos

Link Copied

1 Reply
ZiYing_Intel
Employee
‎03-06-2023 07:31 PM
553 Views

Hi,


Thanks for submitting the issue.

Would you mind to share your .qar file? So that I can try to debug the issue from my side.


Best regards,

Zi Ying


0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.