FPGA reconfiguration for OpenCL logic

[YYama47]

Hello,

I am Yoji Yamato in Japan.
I used Dell PowerEdge R740 with Intel FPGA PAC D5005 (Intel FPGA Stratix).

I would like to verify FPGA reconfiguration.
I implemented FPGA logic by OpenCL.
When I reconfigurate FPGA logic written by OpnCL to other FPGA logic written by OpenCL, how should I do ?
I think "Partial Peconfiguration" and "Remote System Upgrade" can be used but I cannot find the way to reconfigurate with OpenCL.

[HRZ]

You don't need to do anything in particular. As long as you have set up your board correctly and have followed the Intel's documentation to write your host code, compile your kernel offline, and load the compiled binary at run-time, the clCreateProgramWithBinary() in your host code will automatically reconfigure the FPGA at run-time through PCI-E.

[YYama47]

Thank you for your reply.

I would like to verify reconfiguration from one OpenCL application to another OpenCL application.
Currently, I am looking for a way to run multiple applications (IPs) in parallel without conflict. Can clCreateProgramWithBinary() run multiple applications in parallel ?

[YYama47]

Hello,

How about this one ?
Let me update the question.

I would like to verify "dynamic-reconfiguration" from one OpenCL application to another OpenCL application.
Currently, I am looking for a way to run multiple applications (IPs) in parallel without conflict. Can clCreateProgramWithBinary() run multiple applications in parallel ?
If there are any samples of dynamic-reconfiguration from one OpenCL application to another OpenCL application, could you tell me the sample information ?
I only found a reconfiguration sample of LED but it is not written by OpenCL.

Best regards,

Yoji 

[HRZ]

Please check the discussion in this thread:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-OpenCL-handles-multiple-accelerators-on-FPGA/td-p/30352

You can have multiple kernels/IPs in one .cl file, which will turn into one bitstream, and you can run the kernels in parallel by using multiple OpenCL queues without needing dynamic reconfiguration. The FPGA area will be shared between the different kernels/IPs in this case. Alternatively, you can also have multiple IPs in different .cl files to avoid sharing of FPGA area, synthesize each .cl file separately, and load all of the bitstreams at run time. Whenever a kernel associated with a specific bitstream is called, the OpenCL run-time will automatically reconfigure the FPGA with the associated bitstream.

[YYama47]

Thank you for your information.

I have acquired the information of this question.

[BoonBengT_Intel]

Hi @YYama47,

Thank you for posting in Intel community forum and hope all is well.
Just checking in to see if there is any further doubts in regards to this matter.
Hope we have clarify your doubts.

Best Wishes
BB

[BoonBengT_Intel]

Hi @YYama47,

Greetings, as we do not receive any further clarification on what is provided, we would assume challenge are resolved. Hence thread will no longer be monitored. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes
BB