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fpgalearner
Beginner
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Fluctuation in the execution time results for OpenCL applications on Stratix V FPGA board.

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Hi,

I have a concern with the execution time results that I get from the Intel SDK Profiler. I am running rodinia applications using the Intel SDK HLS 16.0 on the Stratix V board. The profiler reports execution time results fluctuating in the order of ~ 20-30ms. I have tested and observed the same pattern for a number of applications including the vector add example that is included in the test example, although the results I get are right. Can anyone please help with why I see such results?

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HRZ
Valued Contributor II
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The profiler is not made for timing measurement, it is made for detecting bottlenecks. Since the profiler dumps data onto the disk during execution, it could cause significant overhead and fluctuation in the run time. Use a host side timer (e.g. gettimeofday()) or the "clGetEventProfilingInfo()" function provided by the OpenCL standard to measure run time instead. 20-30 ms of fluctuation could be normal if run time is in the order of multiple seconds. Furthermore, for short benchmarks with random memory accesses, run time fluctuation could be high due to variable run-time scheduling of memory accesses.

 

P.S. You might want to take a look at this repository which already has some of the Rodinia benchmarks ported for Intel FPGAs and already has host side timers in place:

 

https://github.com/fpga-opencl-benchmarks/rodinia_fpga

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HRZ
Valued Contributor II
101 Views

The profiler is not made for timing measurement, it is made for detecting bottlenecks. Since the profiler dumps data onto the disk during execution, it could cause significant overhead and fluctuation in the run time. Use a host side timer (e.g. gettimeofday()) or the "clGetEventProfilingInfo()" function provided by the OpenCL standard to measure run time instead. 20-30 ms of fluctuation could be normal if run time is in the order of multiple seconds. Furthermore, for short benchmarks with random memory accesses, run time fluctuation could be high due to variable run-time scheduling of memory accesses.

 

P.S. You might want to take a look at this repository which already has some of the Rodinia benchmarks ported for Intel FPGAs and already has host side timers in place:

 

https://github.com/fpga-opencl-benchmarks/rodinia_fpga

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