Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, DLA, Software Stack, and Reference Designs
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
424 Discussions

How can I know if e10_avl_st_gen.v and e10_avl_st_mon.v in filelist.txt be included in compilation of original vendor design example eth_e2e_e10?

User1582192733150209
406 Views

Hello Sir/Madam,

 

I am running the original vendor design example eth_e2e_e10 on Intel PAC aria10gx.

 

I wonder the 2 design file  e10_avl_st_gen.v and e10_avl_st_mon.v in filelist.txt  were not included in the design compilation.

 

what I have done was

I open the Quartus GUI and open the /root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/build_synth/build/dcp.qpf.

 

I could located the GEN and MON module in the hierarchy view of grren_bs, and found the relative design files been used in this project were in below location

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_gen.v

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_mon.v

 

I have check the comparing the design file between avalon_st_gen.v and  e10_avl_st_gen.v, they are similar but not exactly same.

 

Could you tell me  if e10_avl_st_gen.v and e10_avl_st_mon.v in filelist.txt be included in compilation of original vendor design example eth_e2e_e10? if not ,can we just remove them from filelist?

 

thanks

 

Jim

 

 

 

0 Kudos
17 Replies
User1582192733150209
267 Views

gen_mon.JPG

 

filelist.JPG

JohnT_Intel
Employee
267 Views

Hi,

 

You need to include it and it cannot be removed. It is used in the design

User1582192733150209
267 Views

Hi JohnT,

 

May I know more detail about that ?what that 2 files for ?

and what is the diffrentce comparing to below 2 files

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_gen.v

/root/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/eth_e2e_e10/hw/rtl/e10/eth_traffic_controller/avalon_st_mon.v

 

thanks

 

jim

 

JohnT_Intel
Employee
267 Views

Hi,

 

Avalon_st_gen.v is the Avalon ST Generator and Avalon_st_mon.v is the monitor IP. It is a IP used to performed traffic validation on your system.

 

The e10_avl_st_gen.v and e10_avl_st_mon.v is the high level design which will call the the Avalon_st_gen.v and avalon_st_mon.v file in order to incorporate the Ethernet validation using the Avalon ST packet.

 

User1582192733150209
267 Views

Hi JotnT,

 

Thanks for your feedback.

May I know where can I find this parent-child relationship between these similar but diffrent module?

I have fond the parent module of Avalon_st_gen.v and eth_std_traffic_controller_top, is eth_std_traffic_controller_top from the synthesis view under ccip_std_afu/prz0/lp0.[0].eth[0]/gen_mon_inst/

 

I have not found the top module of avalon_st_gen being installed in e10_avl_st_gen.v. Also I have not found the parent module of e10_avl_st_gen.v, not sure if they visitble for customer?

and not sure how the e10_avl_st_gen.v call the avalon_st_gen without installing it in source code?

 

I am bit confused about that file.

I have compared them, found the very similar even in sub modules architecture.

 

many thanks

 

Jim

JohnT_Intel
Employee
267 Views

Hi,

 

You can find the module in "eth_e2e_e10/hw/rtl/e10/eth_traffic_controller" directory and "eth_e2e_e10/hw/rtl"

User1582192733150209
267 Views

Can I have a call meeintg with you for several minutes? thanks,Jim

jimlinmake@hotmail.com

JohnT_Intel
Employee
267 Views

May I know what do you want to discuss?

User1582192733150209
267 Views

to clarify the question and anwser, because with your anwser I still don not undersdand it clearly

JohnT_Intel
Employee
267 Views

I would recommend you to use Quartus to check the design hierarchy and RTL viewer to see how it is implemented.

User1582192733150209
267 Views

I have done that and foun e10_avl_st_gen.v and e10_avl_st_mon.v are not in the hirrachy and RTL view, taht is way I ask this question.

 

thanks

 

Jim

User1582192733150209
267 Views

 

I have done that and foun e10_avl_st_gen.v and e10_avl_st_mon.v are neither in the hierachy , nor in RTL view, that is why I ask this question.

 

thanks

 

Jim

JohnT_Intel
Employee
267 Views

Hi,

 

After further checking and investigation, the e10_avl_st_gen and e10_avl_st_mon is for simulation purpose. while the avalon_st_gen and avalon_st_mon is for hardware implementation.

User1582192733150209
267 Views

thanks for your help and support.

if so, maybe we can remove them from filelist without influcing the whole implementation.

 

Best regard

 

Jim

JohnT_Intel
Employee
267 Views

Hi,

 

You may remove it but if you need to performed simulation in the future then you will no longer able to performed it until you add it back.

User1582192733150209
267 Views

Hi JohnT,

 

Thanks for your help and support.

 

Jim

JohnT_Intel
Employee
267 Views

Glad to be able to help you

Reply