Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, DLA, Software Stack, and Reference Designs
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How to create an Avalon Memory Maped FIFO with different input and output data widths in the Platform designer?


I am trying to transfer data from a PC to a FIFO on the FPGA. I am using PCIE DMA for the transfer. That data is then used in calculations, and the results are stored in another FIFO that then has to be read form the PC. I am experimenting with several setups but none of them have worked so far:

(1)Use instances of the avalon slave template in the platform designer, connect them to the PCIE DMA, and export the user signals to FIFOs inside my verilog modes.

(2)Use an Avalon MM FIFO in the platform designer connect it to instantces of the Avalon master template, and export the conduits of those templates to the part in my verilog code that needs to communicate with the FIFOs.

(3)If all else fails I might try using PIOs.


Insight on whether one or none of these methods is correct would be appreciated. But my question here is about method 2. I only know how to trafer data between in the PC and the FPGA 32 bits at a time, using PCIE_Read/Write32() which comes in a DE5-net user-manual demo. However, on-chip I need to procecess the data 2,4, and 128 bits at a time at different points so I wanted to use dual clock fifos with different data widths, which is possible in Quartus, but I can't find out how to do it in platform designer. is there a way?

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Hi Sir,


The 32bits read/write is 1 Dword. For converting the data width, you may consider using Avalon ST data format adapter in the platform designer, if not, you may need to create your own custom component for your design requirement.


Regards -SK