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Intel Opencl FPGA memory bandwidth


I am using Arria 10 development kit board with memory bandwidth of 19.2 GB/s. But for my design after I compile I get optimal bandwidth of 13GB/s, is there a way to achieve memory bandwidth of 19.2GBs ?

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Valued Contributor II

Having only one 512-bit burst coalesced aligned memory access in your kernel running at 300 MHz with interleaving disabled should give you ~95% of theoretical peak bandwidth. This is certainly not a realistic case for majority of designs but the memory controller is so primitive, any other case will give you lower (probably much lower) memory performance.


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