Intel Opencl FPGA memory bandwidth

[ADua0]

I am using Arria 10 development kit board with memory bandwidth of 19.2 GB/s. But for my design after I compile I get optimal bandwidth of 13GB/s, is there a way to achieve memory bandwidth of 19.2GBs ?

[HRZ]

Having only one 512-bit burst coalesced aligned memory access in your kernel running at 300 MHz with interleaving disabled should give you ~95% of theoretical peak bandwidth. This is certainly not a realistic case for majority of designs but the memory controller is so primitive, any other case will give you lower (probably much lower) memory performance.

The discussions in this thread might also help you:

https://forums.intel.com/s/question/0D50P00003yyTK3SAM/global-memory-access-512-bit-width-constrain?language=en_US

There are more discussions on the issue of memory bandwidth if you search the forum.