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I tried to compile design for two Stratix V devices: 5SGXEA7K2F40C2
and 5SGXEABK2H40C2. And the result is the same even though these devices have different parameters. And actually the design always compiles for 5SGSD8 as I see from available resources. How can I fix it?
i++ Version18.1.0 Build 625
i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed -march=5SGXEA7K2F40C2 fpga_main.cpp -o bfpga
or
i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed -march=5SGXEABK2H40C2 fpga_main.cpp -o bfpga
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Hi
Sorry for the late response, Hope you are staying safe
Can you provide the results of the command with options
--debug-log and -v included
Like
- i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed --debug-log -v -march=5SGXEA7K2F40C2 fpga_main.cpp -o bfpga
- i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed --debug-log -v -march=5SGXEABK2H40C2 fpga_main.cpp -o bfpga
Thanks and Regards
Anil
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Hi
Please check the following also
In Each case please analyze the generated quartus_compile.qpf file in bfpga.prj/quartus with the Quartus GUI to see what part is in the QSF.
That would also help to clarify. Please try that first and let us know.
Thanks and Regards
Anil
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We do not receive any response from you to the previous question/reply/answer that I have provided.
Please post a response in the next 15 days to allow me to continue to support you.
After 15 days, this thread will be transitioned to community support.
The community users will be able to help you with your follow-up questions
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