Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
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i++ always compiles for different device

SKaza4
Novice
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I tried to compile design for two Stratix V devices: 5SGXEA7K2F40C2

and 5SGXEABK2H40C2. And the result is the same even though these devices have different parameters. And actually the design always compiles for 5SGSD8 as I see from available resources. How can I fix it?

 

i++ Version18.1.0 Build 625

 

i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed -march=5SGXEA7K2F40C2 fpga_main.cpp -o bfpga

or

i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed -march=5SGXEABK2H40C2 fpga_main.cpp -o bfpga

 

 

 

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SKaza4
Novice
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Annotation 2020-03-23 121521.png

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AnilErinch_A_Intel
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Hi

Sorry for the late response, Hope you are staying safe

Can you provide the results of the command with options

--debug-log and -v included

Like

  1. i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed --debug-log -v -march=5SGXEA7K2F40C2 fpga_main.cpp -o bfpga
  2. i++ -I/home/sk/intelFPGA/18.1/hls/include --fpc --fp-relaxed --debug-log -v -march=5SGXEABK2H40C2 fpga_main.cpp -o bfpga

Thanks and Regards

Anil

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AnilErinch_A_Intel
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Hi

Please check the following also

In Each case please  analyze the generated quartus_compile.qpf file in bfpga.prj/quartus with the Quartus GUI to see what part is in the QSF.

That would also help to clarify. Please try that first and let us know.

Thanks and Regards

Anil

 

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AnilErinch_A_Intel
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