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Hardware Acceleration and Segment Routing over IPv6 (SRv6) help CoSPs Optimize and Simplify their Networks

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Communications service providers (CoSPs) are seeking ways to differentiate themselves and to enhance their customers’ experiences in the fast-evolving telecommunication (telco) market—all while keeping costs under control. Exponential traffic growth and constant pressure to add more services and subscribers can tax legacy infrastructure, forcing CoSPs to constantly optimize and simplify their networks. Many CoSPs have deployed network functions virtualization (NFV) in an effort to optimize their networks. However, an influx of new subscribers and growing data loads consume a growing number of CPU cycles simply to route traffic, which leaves fewer compute resources to run actual containerized network functions (CNFs) and virtualized network functions (VNFs) that CoSPs want to support. The end result: suboptimal performance and the need for more hosts. To help overcome these challenges, CoSPs are turning to technologies such as hardware acceleration and segment routing over IPv6 (SRv6).

SRv6 helps address the requirements of NFV and software-defined networking (SDN) architecture. It provides a unified solution for networking programmability, service function chaining (SFC), protocol simplification, traffic engineering, and mobile and fixed network convergence.

An SRv6 solution from Intel and HCL overcomes network bottlenecks and achieves up to 3x savings in processor cores by offloading low-level SRv6 processing to the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000. The card is reprogrammable and delivers the flexibility that CoSPs need to support new networking workloads. HCL has built an optimized architecture that enhances network throughput and predictability while reducing latency by taking advantage of the plugin-based framework of vector packet processing (VPP) and by offloading CPU-intensive operations to the Intel FPGA PAC N3000.

The solution frees up CPU cores by offloading CPU-intensive segment-routing functions to the Intel FPGA PAC N3000, which means that four CPU cores in the hardware-assisted solution can deliver comparable performance to 12 cores running a software-based SRv6. That’s a 3x savings in CPU cores as shown in the graphic below.1




Freed CPU cores and cycles can be dedicated to vital CNF workloads running on that networking infrastructure instead of networking infrastructure. The solution’s small footprint can help reduce power and cooling costs. It is available for both VNF-based environments through VPP support and CNF-based environments (and Kubernetes) through Contiv-VPP support.

The HCL solution based on the Intel FPGA PAC N3000 supports the following SRv6 endpoint behaviors, all of which enable SFC, L2VPN, and L3VPN:


  • Static proxy (End.AS)

  • Dynamic proxy (End.AD)

  • Decapsulation and cross-connect (End.DX)

  • Decapsulation and specific table lookup (End.DT)


For more technical details, see the new Solution Brief titled “Accelerate SRv6 Processing.” (Click on the link to download the Solution Brief.)



Notices and Disclaimers

1 Based on HCL testing on January 21, 2020. Test environment configuration: Intel® Xeon® Platinum 8180M processor (2.50 GHz, 56 cores), CentOS 7.6, kernel 3.10.957, Contiv-VPP v3.3.2.1 (VPP 19.08), Data Plane Development Kit (DPDK) v19.05, Ixia Network Tester, Intel FPGA PAC N3000, with up to four virtual machines (VMs) running L3 Forwarding; test topology: traffic generator connected back-to-back to the server host through optical cables. QSFP28 100 Gb port is broken out into 4 x 25 Gb; only two of them are used. For more information about testing, contact HCL.

Performance results are based on testing as January 21, 2020, and may not reflect all publicly available security updates.

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