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Intel’s new technology puts ADCs and DACs operating at 64 Gsamples/sec into packaged FPGAs

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Intel has announced new technology that combines FPGA die with high-speed analog chiplets that incorporate both ADCs and DACs operating as fast as 64 Gsamples/sec. With analog sampling rates that fast, this technology represents a revolutionary step towards providing direct RF capability for radar, test & measurement, and wireless communications systems. This heterogeneous system-in-package technology leverages Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and the open standard Advanced Interface Bus (AIB) to seamlessly integrate the ADC/DAC chiplet with the FPGA die.

Beamforming systems used in radar and other mission critical applications are currently designed with 32 or more antenna elements sharing a single analog converter. This new architecture significantly increases algorithm complexity and requires substantially more digital signal processing (DSP), memory, and logic FPGA resources. As a result, these systems are now transitioning to wider bandwidth, all-digital designs, where each antenna element connects directly to an ADC and DAC. This all-digital architecture reduces the amount of data transmitted through a system and speeds the transmission of actionable information to enable more rapid decision making by placing required computing resources closer to the sensor.

Intel’s state-of-the-art heterogeneous packaging technology can connect chiplets from different processing nodes, including the ADC/DAC chiplet, to the FPGA fabric. This packaging technology connects chiplets using thousands of wires, each operating at 1 Tbps, using EMIB interconnect technology and the AIB physical layer protocol. Combining the high-speed converters with the FPGA in one packaged device eliminates the need for SERDES or JESD204 package-to-package interconnects and significantly reduces power consumption.

The first Intel offering to employ this technology will feature an analog data converter with input sample rates up to 64 Gsamples/sec. This offering will combine high-performance ADCs and DACs with a high-density, high-performance FPGA fabric and other dedicated transceiver chiplets in one package.

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