Top level-design

[ShashwatS]

I have Top level-design error on this Verilog code which is for a c-element.

C-element output= OR( AND(A,B), AND(B, output), AND(A, output)). So basically a feedback is used. 

Can you please respond to this issue as soon as possible?

[JesusE_Intel]

Hi ShashwatS,

This question does not seem to be related to Intel® Edge Software Device Qualification (ESDQ) package. Could you please confirm which Intel product you are using so I can route your question to the correct team?

Regards,

Jesus

[JesusE_Intel · Accepted solution]

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