Embedded Connectivity
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I210 firmware and programming tool

AliUS
Beginner
1,343 Views

Hello,

We designed a custom hardware board using Intel I210 ethernet controller in order to add a second ethernet interface to our product. In our design, we use Raspberry Compute Module 4 as host device. When we run "lspci -vvv" command in our device, we get the following log.

 

01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Unprogrammed (rev 03)
Subsystem: Intel Corporation I210 Gigabit Unprogrammed
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Interrupt: pin A routed to IRQ 0
Region 0: Memory at 600000000 (32-bit, non-prefetchable) [disabled] [size=8M]
Region 2: I/O ports at <unassigned> [disabled]
Region 3: Memory at 600800000 (32-bit, non-prefetchable) [disabled] [size=16K]

 

Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [70] MSI-X: Enable- Count=5 Masked-
Vector table: BAR=3 offset=00000000
PBA: BAR=3 offset=00002000
Capabilities: [a0] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <16us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Via WAKE#
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Capabilities: [140 v1] Device Serial Number 00-a0-c9-ff-ff-00-00-00
Capabilities: [1a0 v1] Transaction Processing Hints
Device specific mode supported
Steering table in TPH capability structure
Capabilities: [1c0 v1] Latency Tolerance Reporting
Max snoop latency: 0ns
Max no snoop latency: 0ns

 

We think the first line of the log suggests that I210 controller is unprogrammed and we need to upload a firmware to it. If you think this is the case, can you please guide us how to access the firmware and the tool required to flash the nvm of the IC.

 

Best regards,

Ali

 

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3 Replies
CarlosAM_INTEL
Moderator
1,316 Views

Hello, @AliUS:

Thank you for contacting Intel Embedded Community.

We suggest verifying that the affected implementation fulfills the requirements stated in the answers to questions 2.23,  2.14, 2.15, and 2.16, on pages 9 and 8 of the Intel® Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) that can be found in the following website:

https://cdrdv2-public.intel.com/334026/ethernet-controller-i210-i211-faq.pdf

Best regards,

@CarlosAM_INTEL.

 

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AliUS
Beginner
1,302 Views

Hello @CarlosAM_INTEL,

Thanks for the reply. I can confirm that our design fulfills the power up sequence requirements stated in 2.23 of the FAQ document. We also checked the PCI ID of the device and it is 0x1531, which, according to 2.23, indicates an unprogrammed device. We don't have access to the tools and files stated in 2.14, 2.15 and 2.16. I understand that this requires a privileged account. How can I update my account to gain a privileged access?

Best regards.

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CarlosAM_INTEL
Moderator
1,280 Views

Hello, @AliUS:

 

Thanks for your reply.

You should request the update of your account to Intel Developer Zone Premier by filling out the form stated on the following website: 

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html 

You should use a business email address to evade any inconvenience. Please avoid the free email provider's address (such as the one provided by Hotmail, Gmail, Yahoo, or others). you can confirm this information and more details on the following website:

https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html 

Best regards,
@CarlosAM_INTEL.

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