I210 programming part 4

[WBall]

In a previous answer,  it was ​stated that the I210 programming pins ( NVM_CS, SI, SO and SK  ) are not able to be tri-stated.   After looking at the I210 datasheet,  I found that in  section 2.3.2 FLASH,  it lists these pins as type" T/s" , meaning tristate-able.   Then in section 4.4.2,  Disabling Both LAN and PCIe Function Device off,    it says  " While in disable mode,  the PCIe is in L3 state.  The PHY is in power down mode.  Output buffers are tri-stated."

My question - Do these tri-stated output buffers include the  programming pins ( NVM_CS, SI, SO and SK ) ?   Please confirm.

Thank you

Whitney Ballard

[CarlosAM_INTEL]

Hello, @WBall​:

Thank you for contacting Intel Embedded Community.

We apologize for the confusion.

These are tri-state pins that can be configured when they are disabled. You can confirm this information in section 4.4.2, on page 143 of the Intel(R) Ethernet Controller I210 Datasheet document # 333016 that can be found at:

https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i210-ethernet-controller-datasheet.pdf

Best regards,

@Mæcenas_INTEL​.