We are designing our own PCB and use i210IS chip.
So, we need to know what type of differential input clock does PECLKp/n signals use? LVDS? HCSL or another?
Looking forward your answer!
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Can you confirm if this current post from you is related to this previous post: https://community.intel.com/t5/Embedded-Connectivity/I210IS-PECLKx-standard/td-p/1328121/jump-to/fir... or if it is a different issue?
If you check the Intel I210 datasheet: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i210-cs-cl-ethernet-controll...
Section 22.214.171.124, you can read the following:
The input clock for PCIe must be a differential input clock in frequency of 100 MHz. For full specifications please check the PCI Express* 2.0 Card Electro-Mechanical (CEM) Specification (refclk specifications for Gen 1 ).
So the answer to your question is on the PECLKp/n signals follow the PCI Express® Card Electromechanical Specification Revision 1.1 for the Refclk.
Now, you will have to confirm this on your side, but at least for Revision 2.0 of the CEM specification: https://www.cl.cam.ac.uk/~djm202/pdf/specifications/pcie/PCI_Express_CEM_r2.0.pdf the Refclk is stated to be low voltage swing differential clocks.
If you need more details, as mentioned earlier, access to the Intel Resource and Design Center is recommended.