i210 with external SGMII PHY on external MDIO bus

[FCham]

Hi everyone,

we are using a i210IS on our board, with an external copper PHY, connected through SGMII and MDIO.

The NVM has been successfully programmed with Dev_Start_I210_Sgmii_NOMNG_8Mb_A2_3.25_0.03.

The host is WinCE7, using the latest Intel Driver.

During the driver start-up, we realised that the external MDIO bus was used in I2C mode, so the relevant changes were made to both the Driver code and NVM bit settings.

Now, the i210 communicates to the PHY on the external MDIO bus, in MDIO mode.

However, everytime the i210 starts a cycle on the MDIO bus, it stops the clock (MDC) in the middle of the transaction.

The preamble is shifted out, then the command, but then the clock is stoppped. After a while, the READY bit is activated, along with the ERROR bit.

We suspect a Power Management issue, did some tests with different settings, but we always get the same behavior.

Any clue?

[CarlosAM_INTEL]

Hello, FCh:

Thank you for contacting the Intel Embedded Community.

We suggest you verify that your design fulfills with the suggestions stated in the answers to the questions 2.9, 2.13, 2.16, 2.22, 2.23, 2.29, and 2.30; on pages 6, 7, 8, 9, 10, and 11 of the http://www.intel.com/content/dam/www/public/us/en/documents/faqs/ethernet-controller-i210-i211-faq.pdf Intel(R) Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) document # 335346.

By the way, if the problem persists, we would like to address the following questions:

Could you please tell us if the affected design is a third party one or it has been developed by you? In case that it is your project, could you please tell us if it has been developed based on the suggestions stated in the Ihttps://edc.intel.com/Link.aspx%3Fid%3D8393 ntel(R) Ethernet Controller I210: Design Guide document # 513305, https://edc.intel.com/Link.aspx%3Fid%3D8390 Intel(R) Ethernet Controller I210-AT/IT: Layout Review Checklist document # 495298, and https://edc.intel.com/Link.aspx%3Fid%3D8391 Intel(R) Ethernet Controller I210-IS: Layout Review Checklist document # 495299? Also, could you please confirm us if it has been verified by Intel?

Thanks in advance for your collaboration to solve this inconvenience.

Best regards,

Carlos_A.

[FCham]

Hi Carlos, thanks for this fast reply!

I rechecked all the documents, in case there was something new...

The design complies to the points but it has not been reviewed by Intel.

[FCham]

Carlos, here is a little more information:

After Hard Reset, the i210 does an incomplete READ to PHYADD 0 and REG 0, not under software control.

Then when the driver loads, the first read is under software control, to PHYADD0, REG 2.

[FCham]

Hi Carlos, here is more data, with scope shots.

** I had problems including the images, so here is a link to the images:

http://Tests MAC https//explora.egnyte.com/fl/hEeHVfXMpW Tests MAC https://explora.egnyte.com/fl/hEeHVfXMpW

01 - The first MDIO cycle, done by the MAC coming out of RESET. The sequence is correct, but stops and goes. The cycle stops for goods after the MAC has driven the Preamble, the Opcode, the PHY address and the Register address.

02 - The end of the same cycle in detail. It shows the last Register address bits being driven out and the 2 'turnaround' clock cycles where the MDIO signal is tri-stated.

03 - The first software initiated Read Cycle on the MDIO Bus.

04 - The end of that cycle in detail.

Since my last post, I have verified that the clock signal provided to the MAC is good. It is generated by an oscillator, through the recommended capacitive divider. I measure a very steady square wave at 25MHz, with 1,4V amplitude. I also tried a different divider, which provided a larger 2,0V amplitude on XTAL1, without any change on the behavior.

What would you suggest to do if we want to disable the power management and run some tests?

Thanks for your help!

[CarlosAM_INTEL]

Hello, FCh:

Thanks for your replies.

We suggest you clear APM and APM PME to disable power management.

By the way, could you please tell us which bits have been changed to enable MDIO?

Thanks in advance for your cooperation.

Best regards,

Carlos_A.

[FCham · Accepted solution]

Hi everyone, I just found the problem.

Our PHY is not properly started, so when the MAC tries to communicate with it through MDIO, it does not respond at all.

It is clear now that when the MDIO master initiates a cycle, it will drive the preamble, the Opcode, the adresses, and then will monitor the bus during the Turnarond cycles. If the bus is not pulled high, then low during the Turnaround cycles, the master assumes there is no one to answer the request, and stops the cycle.

Once I get the PHY to start correctly, the cycles are completed correctly.

To enable the External MDIO, I only changed Word 0x24 from 0x42A0 to 0x42A4, so that MDICNFG.Destination is set right after RESET.

With this bit set, the driver correctly steers the communication to the external bus, in MDIO mode.

Best regards!

[DKlet]

When you changed bit 2 in 0x24, did you make the change in the hex file? If so, did you then use EEUpdate or Lanconf to program it into the part? I'm trying to do something similar, but I can not seem to get the change to write properly to the Flash chip. Thanks

[CarlosAM_INTEL]

Hello, Daniel_K:

Thank you for contacting Intel Embedded Community.

The flash word can be edited with Lanconf directly. Due to this fact, edit a file then upload it unnecessary using Lanconf.

By the way, after programming the flash, an AC cycle is required.

We hope that this information may help you.

Best regards,

Carlos_A.