i210AT magnetics center tap configuration

[wmueller]

Following the documentation and evaluation board of the i210AT, each of the 4 center taps of the magnetics, on the phy side, need a capacitor to GND (typically 100nF/X7R). And the center taps are connected. Because of the voltage-mode transmit drivers of the i210AT, no connection of the linked center taps to a supply is needed/allowed. A position for an optional capacitor on the linked center taps is recommended but not placed usually.

For most other phys with voltage-mode transmit driver for the magnetics, a connection of the center taps is not needed or not allowed. The difference in the bias voltage on the center taps could result in unwanted or critical cross currents.

Is the connection/link of the center taps for the i210AT really needed?
Do I have any drawback, if I use only a capacitor to GND on each center tap, without the link between?

The need of the connection between the center taps reduces the choice of MagJacks. Especially if the style is predetermined by constructional and place constraints. As it is in my case also, where I have multiple ethernet controllers and phys on the same design, I need different types of MagJacks.

[AlfredoS_Intel]

Hi Wmueller,

Thank you for posting in our Intel® Ethernet Communities Page.

Please allow us some time to check on your concern.

We will get back to you no later than 3 business days from now.

Best Regards,

Alfred S

Intel® Customer Support

[AlfredoS_Intel]

Hi Wmueller,

Thank you for waiting for our update.

While we were checking, this question came into mind which will help us find a solution for your issue:

1. It looks like you are building a custom design system.  Are you incorporating the I210 chip to an Intel Field Programmable Array (FPGA), System on Chip (SOC), Complex programmable logic device (CPLD)?

We look forward to your reply. Should we not get your reply, we will follow up after three business days.

Best Regards,

Alfred S

Intel® Customer Support 

[wmueller]

Hi Alfred S

The system is based on a SOM (System on Modul, ARM, iMX8M-Mini). We need 2 Ethernet Interfaces with own MAC.

The SOM delivers one PICe lane, where we connect the i210AT.
Beside of that, the SOM delivers an MDI interface for the second Ethernet interface. MAC and Phy (AR8033) are part of the SOM.
We use this configuration on other designs too and it works well. There, we could use a MagJack, where all the phy-sided connections of the magnetics are separate accessible (also the center taps).
The difference in the connection (center taps) for the i210AT and AR8033 could by handled on the PCB.

On the new design, we have special constraints for the MagJack, on space and shape (vertical).
MagJacks with separated center taps are hard to find (to less pins). We would need different types, with different internal configuration, if the i210AT would not work with the "standard configuration" for voltage-mode transmit drivers.

Best regards,
wmueller

[AlfredoS_Intel]

Hi Wmueller,

Thank you providing those information.

Please allow us some time to check on this. 

We will get back to you no later than 3 business days from now.

Best Regards,

Alfred S

Intel® Customer Support 

[AlfredoS_Intel]

Hi Wmueller,

Thank you for waiting for our update.

Since your issue is regarding an embedded design, we need to route this thread to the correct group so you will be better assisted by the proper team.

Please wait for their reply within 1 to 2 business days.

Best Regards,

Alfred S

Intel® Customer Support

[CarlosAM_INTEL]

Hello, @wmueller:

Thank you for contacting Intel Embedded Community.

You can find the guidelines to implement a design without magnetics in the Intel(R) 82580/I350/I210 Magnetic-Less LAN Design Guide document # 480093. You can find this document when you are logged into your Resource & Design Center (RDC) privileged account in the following website:

http://www.intel.com/cd/edesign/library/asmo-na/eng/480093.htm

The RDC Account Support form is the channel to process your account update request or any inconveniences with the provided website. It can be found at:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[wmueller]

Hi Mæcenas

I will check the reference document, as soon it got access to it.

But I do not look for a solution for a Magnetic-Less i210AT Design.

I would like to know, if the connection/link between the 4 phy-sided center taps is really needed (beside the capacitor on each center tap connected to GND?
Does it work also with just a 100nF capacitor on each center tap to GND.

Best regards,
Walter

[CarlosAM_INTEL]

Hello, @wmueller:

Thanks for your reply.

The information stated in the documentation is tested and validated by Intel. However, in case you want to implement something not included in the documents, it should be tested and validated on your own.

Best regards,

@CarlosAM_INTEL.