Atom C3000 DDR4 point-to-point topology model

[AlexMo]

Hi,

we are familiar with the 557297 'Intel Atom® Processor C3000 Product Family DDR4 HSPICE* Signal Integrity Model' and we have managed to use it for studiyng of the MBERE approach, modelling environment, etc. There is only one problem here - we are using point-to-point DDR topology on our board while the 557297 model is designed for a T-topology, so this model can't be used for our board SI check. Please prompt, is there a similar model for a point-to-point topology? Or maybe some recommendations regrding how to transform the 557297 model to a point-to-point type exist?

thanks in advance,

Alexander

[CarlosAM_INTEL · Accepted solution]

Hello, @AlexMo:

Thank you for contacting Intel Embedded Community.

You can find the information that may help you in the General Usage of the DDR4 simulation tool document # 553957, Intel(R) Memory Bit Error Rate Executable [Intel(R) MBERE] document # 554422, and Intel(R) Memory Bit Error Rate Executable [Intel(R) MBERE] User Guide document # 569813. You can find these documents when you are logged into your Resource and Design Center (RDC) privileged account on the following websites:

https://cdrdv2.intel.com/v1/dl/getContent/553957

https://cdrdv2.intel.com/v1/dl/getContent/554422

https://cdrdv2.intel.com/v1/dl/getContent/569813

You should fill out the form stated on the following website when you have problems with the provided website or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[AlexMo]

Hi @CarlosAM_INTEL,

thanks are lot for the links you provided, they helped.

Best regards,

Alexander

[CarlosAM_INTEL]

Hello, @AlexMo:

We are glad that our suggestions are useful to you.

Please do not hesitate to contact us again if you have questions related to Intel Embedded products.

Best regards,

@CarlosAM_INTEL.

[Shashi_S]

Hi @AlexMo 

As you mentioned in the post I am also facing the same issue using spice deck for point-to-point topology. As @CarlosAM_INTEL provided few links, I have gone through the link, but could not find solution. Could you please help me in understanding your take away from the links provided.

Regards,

Shashi S

[AlexMo]

Hi @Shashi_S,

one of the documents pointed by links provided by @CarlosAM_INTEL prompts how to recalculate bus segments length. Taking into account that point-to-point connection is just a special case of a T-topology, it is possible just to exclude an unnecessary segments from T. The document prompts how this can be done correctly.

Regards,

@AlexMo 

[CarlosAM_INTEL]

Hello, @Shashi_S:

Thanks for your reply.

Could you please let us know if your questions stated in this thread is related to the following forum?

https://community.intel.com/t5/Embedded-Intel-Atom-Processors/MBERE-1-25-EYE-MASK/m-p/1236975#M4164

Best regards,

@CarlosAM_INTEL.

[Shashi_S]

Hi @AlexMo,

Thank you for sharing your take away.

In the deck we can modify the read and write sections, since DQ and DQS lines has the same length even after T-splits. 

But in the CA bus I used the 1DPC deck, and replaced it with my PCB channel which is point-to-point.
When i simulate for AD/CMD, I observe failing results with large setup margin and no positive hold margin.

(Please note since in point-to-point there is no T-split, no additional 350mils exist )

Is my way of analyzing the set-up is right? Basically can we modify this deck to simulate point-to-point DDR4 DIMM configuration? or is is it only made for validating 2DIMM implementation with T-lines?

Kindly request you to share your experience using the deck. Did you modify the command/address deck to validate point-to-point configuration? Did you observe pass results?

Hi @CarlosAM_INTEL 

Yes, this is related to the same forum. Since @AlexMo has the same issue, I would like to know how did they came up with the solution.

Regards,

Shashi S