Atom E6xx CLK-DQS skew

[idata]

cb Hello,

We are busy with the pcb layout for a Atom E6xx with 8 loads memory.

I am now confused about the length matching between the clock (CLK) and stobe (DQS) lines.

In the datasheet 433311_Rev3.0.pdf on page 36 is mentioned:

The total length of DQS of each byte group must be greater than or equal to CLK + 0.15 in., and must be less than or equal to CLK + 0.5 in.

If I then look at the guideline 325550.pdf (Intel® Atom™ processor E6xx Series – Memory Design Optimization for Small Form Factor), I see on page 23:

The total length of DQS of each byte group must be greater than or equal to CLK - 0.3 in., and must be less than or equal to CLK + 0.2 in.

What should I use for the length of the DQS line matching to the CLK?

Thanks!

[FMcNu1]

Hello

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I hope this helps.

Felix

J. Felix McNulty

Community Moderator (Intel contractor)