Atom E6xx Series - JTAG access control

[TPerm]

I am interested in the ability to restrict access to the JTAG Interface on the Atom E6xx Series. How is this done and is it reversible?

I think the answer to my question could be contained within the following documents but i have had difficulty getting access to them:

CDI document number 433303 - "Intel ®Atom™ Processor E6xx Series – External Design Specification (EDS)"

CDI Document number 436017 - "Intel®Atom™ Processor E6xx Series – Debug Port Design Guide"

I previously made a technical support request to the EDC but received no response...

[Adolfo_S_Intel]

Hello Tom

We are working on this issue, we will reply with more information as soon as possible

Regards,

Adolfo

[Natalie_Z_Intel]

Hello, Tom!

You do have a Privileged EDC account which means you should be able to access these documents:

433303 - http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/atom-e6xx-eds-spec.html?wapkw=433303 http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/atom-e6xx-eds-spec.html

However, 436017 isn't surfacing as it should, so I am working with the publishing team to correct this website issue.

If you need assistance accessing your account (forgot password, login, etc), you can email mailto:edc.support@intel.com edc.support@intel.com or phone them at 1-866-241-9315.

Here is the support page with other options: https://www-ssl.intel.com/content/www/us/en/intelligent-systems/embedded-design-center-contact-us.html Intel® Embedded Design Center Contact and Support. But from what I can see, your account should work fine. Lynn

[TPerm]

Thank you for providing the link to the first document, I have managed to download it successfully.

It however does not answer my question regarding the ability to restrict access to the JTAG Interface on the Atom E6xx Series. Is this contained within the second document or somewhere else?

[Natalie_Z_Intel]

Hi, Tom! The link to document 436017 has been fixed. It is http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/atom-e6xx-series-debug-port-design-guide.html http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/atom-e6xx-series-debug-port-design-guide.html.

Adolfo is checking to see if there is a document that may be more helpful to you that better addresses your question. Stay tuned! LynnZ

[TPerm]

Thanks - I can now access that too.

Unfortunately I'm not sure that either of these documents really answer my question. They both refer to the hardware design of a fully functioning Debug Interface and not how it could be restricted.

Hopefully Adolfo can suggest where I might look instead.

[TPerm]

Have you or Adolfo had any further luck?

[Adolfo_S_Intel]

Hello Tom

Some Intel processors have a security feature in the firmware that disables the access to the CPU using the JTAG interface. I checked out another document that I thought might have the answer but it didn't.

I'm currently in communication with other engineers that are more familiar with this platform to confirm if the Atom E600 series have this feature and how to enable it, I'm awaiting their reply, that hopefully would be positive, or could point us in the right direction.

Regards,

Adolfo

[Adolfo_S_Intel]

Hello Tom

We are still investigating your issue with our Engineers, I apologize for the delay. We will reply back as soon as we find useful information for you.

Regards,

Adolfo.

[TPerm]

Hi AdolfoS,

I was wondering whether you have heard anything back from your Engineers?

Thanks,

Tom

[Adolfo_S_Intel]

Hello Tom

We are still looking into this issue, I'm sorry for the delay.

Regards,

Adolfo.

[Adolfo_S_Intel · Accepted solution]

Hello TomPerman

I have got feedback from our engineers; unfortunately there is not a possibility to disable the JTAG interface via software or firmware.

JTAG interface should be disabled via hardware. Section 9.2.2 of the PDG states that:

If boundary scan is not implemented on the system board, TMS and TDI must be independently bused and pulled up, each with ~10 kO, 5%, 0402 resistors, and TRST_N and TCK must be independently bused and pulled down, each with ~1 kO, 1%, 0402 resistors. TDO must be left open. I can see that several customers have successfully followed these guidelines in their design.

From hardware perspective you need to follow the PDG guidelines to implement JTAG, however Intel does not have any document that implements reversible design.

Best regards,

Adolfo

[TPerm]

Hi,

I assume that your second line should read the following so it doesn't contradict the first line?

"JTAG interface should be disabled via Hardware. Section 9.2.2 of the PDG states that:"

Thanks for your help

Tom Perman

[Adolfo_S_Intel]

Hello Tom

You are right, and I already corrected my reply.

Best Regards,

Adolfo