Documentation for the ValleyView clock generator (DPLL) available?

[OTS]

Hello community,

I would like to programm the clock generator (digital phase locked loop/DPLL) of the graphics circuit "ValleyView" from the platform "Bay Trail" but I cannot find any documentation on the topic.

The documentation about the graphics circuit seems to indicate that there is something called a "sideband message interface" which is used to send data packets (alias "messages") to a subcircuit which is the clock generator. Intel calls this subcircuit "digital phase locked loop" (DPLL).

In earlier versions of Generation X there were GenX-configuration-register which had fields for the P1-, P2-, M1-, M2- and N-values. The graphics circuit "ValleyView" seems to make use of the data packet communication instead of the configuration registers.

But there seem to be 3 undocumented Gen7LC-configuration registers which can be used to create and send the data packets.

Does someone know where to get documentation about

• the side band message interface in general (edit: done, I got the document for this one),
• the 3 undocumented configuration registers to create the messages and
• the clock generator (DPLL)?

Many thanks.

Regards,

Gary

[CarlosAM_INTEL]

Hello, @OTS:

Thank you for contacting Intel Embedded Community.

The Bay Trail available documentation can be found on the following website:

https://www.intel.com/content/www/us/en/products/platforms/details/bay-trail/docs.html

However, we want to clarify that Bay Trail family products are no longer supported, as you may confirm on the following website:

https://www.intel.com/content/www/us/en/support/articles/000022396/processors.html

Best regards,

@CarlosAM_INTEL.

[OTS]

Hello @CarlosAM_INTEL,

thank you for your reply. Unfortunately none of the documents listed on the website linked contains the information requested.

For those interested in this topic who might have the same question as I have:

I found a document from Intel with the title "Providing a sideband message interface for system on chip". It covers the US patent "US 9,213,666 B2". This document describes how the side band messages work in general. However, it does not cover the necessary ValleyView-specific information, like what the unique port numbers for the subcircuits (like the clock generator) are or what the message format is when communicating with the clock generator.

It's something to start with and all I got so far.

[OTS]

Here are some notes of my reverse engineering of the 3 undocumented Gen7LC-configuration registers.

The 3 registers seem to provide an abstract interface to create the messages. They do not seem to allow low level message creation, sending nor receiving.

offsets from the beginning of the MMIO-space:

• beginning of the display engine section in the MMIO-space:
  VLV_DISPLAY_BASE = 18 00 00|h

Gen7LC-configuration registers:

• VLV_IOSF_ADDR = 18 00 00|h + 21 08|h = 18 21 08|h
• VLV_IOSF_DATA = 18 00 00|h + 21 04|h = 18 21 04|h
• VLV_IOSF_DOORBELL_REQ = 18 00 00|h + 21 00|h = 18 21 00|h

fields of the address-channel Gen7LC-configuration register "VLV_IOSF_ADDR":

• field name: | bits:
• --------------------|---------------
• "index" | from 2^31 to 2^0

fields of the data-channel Gen7LC-configuration register "VLV_IOSF_DATA":

• field name: | bits:
• --------------------|---------------
• "payload" | from 2^31 to 2^0

fields of the auxiliary Gen7LC-configuration register "VLV_IOSF_DOORBELL_REQ":

• field name: | bits:
• --------------------|---------------
• "device function" | from 2^31 to 2^24
• "operation code" | from 2^23 to 2^16
• "port" | from 2^15 to 2^8
• "byte enables" | from 2^7 to 2^4
• "BAR" | from 2^3 to 2^1
• "busy" | 2^0

values for the address-channel Gen7LC-configuration register "VLV_IOSF_ADDR":

• VLV_IOSF_ADDR["index"] = write the index of the DPLL-configuration register which is to be read or written to

values for the data-channel Gen7LC-configuration register "VLV_IOSF_DATA":

• VLV_IOSF_DATA["payload"] = write the payload for the DPLL-configuration register or read the payload from the DPLL-configuration register

values for the auxiliary Gen7LC-configuration register "VLV_IOSF_DOORBELL_REQ":

• VLV_IOSF_DOORBELL_REQ["device function"] = The only known value is:

• DPIO_DEVFN = 0x0

• VLV_IOSF_DOORBELL_REQ["operation code"] = There are 2 known values:

• SB_MRD_NP = 0x0 // SB_MRD_NP = side band MMIO read, non-posted
• SB_MWR_NP = 0x1 // SB_MWR_NP = side band MMIO write, non-posted

• VLV_IOSF_DOORBELL_REQ["port"] = Write the unique port ID of the DPLL, which is always:

• IOSF_PORT_DPIO = 0x12

• VLV_IOSF_DOORBELL_REQ["byte enables"] = I have no clue what this field is for. The only known value is:

• 0xF

• VLV_IOSF_DOORBELL_REQ["BAR"] = I have no clue what this field is for. The only known value is:

• 0x0

• VLV_IOSF_DOORBELL_REQ["busy"] = The DPLL will write a "0|b" to this field to indicate, that the read or write has completed. So the only know value for the CPU is:

• SB_BUSY = 0x1

procedure when creating and sending a message:

• to read from a DPLL-configuration register:

1. write the index to the DPLL-configuration register in VLV_IOSF_ADDR.
2. -
3. write the auxiliary data in VLV_IOSF_DOORBELL_REQ.
4. wait untill VLV_IOSF_DOORBELL_REQ["busy"] == 0|d.
5. read the payload from the DPLL-configuration register from VLV_IOSF_DATA.

• to write into a DPLL-configration register:

1. write the index to the DPLL-configuration register in VLV_IOSF_ADDR.
2. write the payload for the DPLL-configuration register in VLV_IOSF_DATA.
3. write the auxiliary data in VLV_IOSF_DOORBELL_REQ.
4. wait untill VLV_IOSF_DOORBELL_REQ["busy"] == 0|d.
5. -

[OTS · Accepted solution]

I still haven't got a documentation about the DPLL, but I made some notes. With these notes it is possible to program the output clock frequency. Maybe someone else is interested, too. So I attached these notes.