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ADL-S / PCH dose not working after SLP_A

doowonjeong
Beginner
907 Views

hello

I am using the ALDER LAKE S platform. (PCH: R680E)

NON-DEEP setting and EC is not used.

The power sequence is all fine, and the SPI also operates for about 500 ms after the voltage is applied.

However, currently my board does not work after SLP_A#.

SLP_S5# is not set to 3.3V.

 

HW STRAP setting of PCH is as follows.

- MAF (GPP_H12 : LOW )

- Disable ESPI ( GPP_C5 : HIGH)

- VCCSPI : 3.3V ( GPP_H18 : LOW )

- BBS ( GPP_I22 : LOW)

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5 Replies
CarlosAM_INTEL
Moderator
890 Views

Hello, @doowonjeong:

Thank you for contacting Intel Embedded Community.

We sent an email to the address related to this account with information that may help you.

Best regards,

@CarlosAM_INTEL.

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jlchu0705
Beginner
561 Views

Hello,@CarlosAM_INTEL:

 

I also experienced the same issue.

Could you email me with information about this issue, too?

 

Thanks!

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CarlosAM_INTEL
Moderator
544 Views

Hello, @jlchu0705:

Thank you for contacting Intel Embedded Community.

We sent an email to the address related to this account with information that may help you.

Best regards,

@CarlosAM_INTEL.

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cc_chen
Beginner
426 Views

Hello,@CarlosAM_INTEL:

 

I also experienced the same issue.

Could you email me with information about this issue, too?

 

Thanks!

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Diego_INTEL
Moderator
389 Views

Hello @cc_chen,

 

Thank you for contacting Intel Embedded Community.

 

The email is referring to using our IPS support to submit a case regarding this issue. 

https://www.intel.com/content/www/us/en/support/articles/000057045/ethernet-products.html

 

Best regards,

 

@Diego_INTEL 

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