Hello Maecenas,
Indeed, the question from my side was exactly in regard to a technical problem.
I already open an support ticket and close it later after receiving a hint that I should post a question into embedded community forum.
Here I will copy my initial information and questions which I asked:
Used PC : Adlink Express-CF-i7-8850H, Com Express Type 6
Used CPU : Core™ i7-8850H
Used PCH : QM370, DeviceID 0xA30C
Used bus : LPC
The problem in short:
We are using Intel LPC bus to communicate with Xilinx FPGA. Our HW and SW which is working with 2nd, 3rd and 5th generation CPU can not establish communication with the FPGA anymore.
What we found so far:
According Intel LPC specification (ver. 1.1 from 2002, document number : 251289-001)
we expect 33MHz clock for the LPC bus (page 9, signal LCLK), but in the reality it is 24MHz for used PCH.
According to the PCH 300 series datasheet vol. 1 (Doc number : 337347-004) in page 184, 24.7 Functional Description is written:
"The PCH LPC interface supports the Low Pin Count Interface Specification. The bus operates at 24MHz clock frequency."
The PCH datasheet vol. 1 refer to LPC bus specification 1.1 in the page 183, 24.3.
We changed the FW of our FPGA to support 24MHz as well, but the communication was not restored.
In the next step we attach a scope to the LPC bus to find out the data, transmitting from the PCH to the FPGA and we found the following:
- the START field (described in 251289-001, page 15) has value 0101 binary (Bits[3:0]) which is reserved according to the LPC specification. This field is generated when we map a memory address and start writing or reading data.
- the Cycle Type Bit (CYCTYPE) is 000 binary for I/O Read and 001 for binary for I/O Write, but we expect 010 binary for Memory Read and 011 binary for Memory Write when we use memory map.
By the way there is a typo in the page 185, doc number 337347-004 : both cycle type bit definitions are for Memory Read, there is no Memory Write).
Questions so far from our side:
- Is there a newer LPC specification which is available?
- What means the value 0101 binary in the START field?
- Where is described the mechanism of getting a memory address which should be set in the LPC Generic Memory Range? It is written "The LGMR memory decode range is 64KB in size and can be defined as being anywhere in the 4GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources." in the PCH datasheet, but in fact BIOS never set this address and we always have to find out which is the correct one.
- Why the read or write requests to a mapped memory (via ioremap) are translated to I/O read/write request on LPC bus?
Best Regards,
Krasimir Kostadinov
Software Engineer
Xpeqt Ltd.
