I made my own board with COFFEE LAKE H.
If I had known the support page before, I would have requested circuit review or artwork review
First I made it based on my own datasheet.
I'll use the FPGA to directly adjust the PCH's power sequence.
While looking at the PDG document, I am writing the power sequence control in Verilog.
I am making a control program referring to the '45.4 Power Sequencing' item in the PDG document.
All of the VCCPRIM power is applied to the PCH, and both SLP_SUS# and SLP_A# come out normally. However, even after pressing the power button, SLP_S5# is always in assert state.
Of course it doesn't go to S4 and S3.
When I press PWRBTN for about 4 seconds, SLP_A# turns off and on, so PCH seems to work.
However, it does not work after S5#.
Could it have something to do with the BIOS?
Both 'Figure 45-3' and 'Figure 45-4' in the '571391_CFL_H_PDG' document appear to access SPI FLASH after S5#.
I understood DSW_PWROK -> RSMRST -> PWRBTN -> S5#, but it stopped from S5#.
The assembled CPU is CL8068404165301S RFEJ and the PCH is FH82CM246 SR40E.
If the process does not work after SLP_A#, please review which part to check from.
Thank you for contacting Intel Embedded Community.
You need to verify that the affected design fulfills the SLP_A# requirements, which are stated in Tables 21-1, 33-5, 33-6, 33-8, 36-1, 45-1, and 45-5; in sections 33.5.1, 36.2.2, 36.2.7, 36.28, 36.2.19, and36.2.20, and; also in Figures 45-3 and 45-4, on pages 321, 378, 380, 381 425, 508, 522, 371, 426, 427, 429, , 513, and 515 of the Coffee Lake H Platform Design Guide (PDG) document # 571391. It can be found when you are logged into your Resource & Design Center (RDC) privileged account on the following website:
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