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I2C bus and EEPROM of the Linux driver design

I am in the development of embedded Linux system based on MPC8250 found in the I2C bus in the embedded system widely used, I2C bus controller type is more, the system provides the operating interface is also very different. I2C bus connected to the slave devices are microcontroller, EEPROM, real-time clock, A / D converter, etc .. MPC8250 processor is through the internal I2C bus controller and these connections in the I2C bus device for data exchange of. Due to the characteristics of the I2C bus, Linux I2C bus device driver designers in the design of the driver using a unique architecture. So that the development of I2C bus device driver and the development of general device driver method is very different. Therefore, the development of I2C bus device driver in addition to the general knowledge of the Linux kernel driver. But also on the I2C bus-driven architecture in-depth understanding. I use the device model AT24C01A EEPROM in the development process to test the I2C bus driver.

2. Overview of the working principle

Before the introduction of I2C bus structure. To figure out two concepts: I2C bus controller and I2C devices. I2C bus controller for the microcontroller or microprocessor to control I2C bus interface, which controls all I2C bus special sequence, protocol, arbitration, timing, here refers to the MPC8250 provides I2C bus control interface. I2C device refers to the I2C bus and microcontroller or microprocessor connected devices, such as EEPROM, LCD driver, etc., here refers to the EEPROM.

In a serial data channel, the I2C bus controller can be configured as either Master or Slave mode. During development, MPC8250's I2C bus controller in the main mode, as the master device; I2C bus connected with the device for the AT24C01A EEPROM, as a slave device. Both the master device and the slave device can operate in the receive and transmit states. The bus must be controlled by the master device, which generates serial clocks to control the direction of the bus and generate start and stop conditions.

2.1 I2C bus controller

I2C uses a two-wire structure consisting of a serial data line SDA and a serial line clock line SCL to exchange data between the external integrated circuit and the controller. MPC8250 I2C bus controller includes the sending and receiving unit, a separate baud rate generator and a control unit. The transmit and receive units use the same clock signal if I2C is the master. Then the clock signal is generated by the I2C baud rate generator; if I2C is a slave, the clock signal is externally supplied.

SDA and SCL are bi-directional and connected to the forward voltage via an external +3.3 V pull-up resistor. SDA and SCL should be high when the bus is in the Idle state.

I2C receive and transmit units are double-buffered, the data from the transmit data register to the shift register to the clock rate output to the SDA line; in the data reception, the data from the SDA line into the shift register, and then enter Receive register.

2.2 I2C bus controller and EEPROM basic operation

I2C bus in the transmission of data in the course of a total of three types of signals, namely: the start signal, the end of the signal and the response signal.

Start signal: SCL is high, SDA from high to low transition, began to transfer data;

End signal: SCL is high, SDA from low to high transition, the end of transmission data;

Acknowledgment: A device that receives data sends a specific low-level pulse to the device that is sending the data after receiving one byte of data. Indicates that data has been received.

When the MPC8250 I2C bus is idle, its SDA and SCL are high, the main device by sending a start signal to start the transmission process. The timing requirement for this signal is that when SCL is high, SDA transitions from high to low. After the start condition. Must be the address byte of the slave device, where the upper 4 bits are device type identifiers (different chip types have different definitions, EEPROM should be 1010), then 3 bits are chip select, the last bit is read and write bit, When 1 is a read operation, 0 is a write operation.

If the master writes data to the EEPROM, the master sends a write request to the EEPROM in the address byte (R / W = 0), followed by the address byte to be followed by the data to be transmitted. After each byte of data is sent, the EEPROM generates an acknowledge and the master monitors the acknowledge. If the EEPROM does not return an acknowledge after a byte has been sent, the master stops sending and generates an end signal .

To read data from the EEPROM, set R / W = 1. After the EEPROM has transmitted one byte of data, the master responds with an acknowledge signal informing the EEPROM master that more data is required and one byte of data is sent for each acknowledge signal generated by the master. The operation is terminated when the master device does not transmit an acknowledge signal and then transmits the end bit.

3.Linux in the I2C bus driver architecture

In a Linux system, the I2C bus driver architecture consists of an I2C bus driver and an I2C device driver for a given I2C bus hardware configuration system. I2C bus driver which includes a specific controller driver and I2C bus algorithm driver. An algorithmic driver is applicable to a class of bus controllers. And a specific bus controller driver to use a certain algorithm. For example, the algorithm i2e-algo-8260 provided in the Linux kernel can be used on the I2C bus controller provided by the MPC82xx family of processors. The Linux kernel provides algorithmic drivers for some common processors such as the MPC82xx family. For I2C devices, basically each specific device has its own basic characteristics. Its drivers generally need to be specially designed.

In the I2C bus driver architecture. Use the data structure Driver to represent the I2C device driver, using the data structure Client represents a specific I2C device. While for the I2C bus

Controller, a variety of bus controllers in the data transmission using a variety of algorithms used, the controller using the same algorithm to provide the control interface may also be different. In the I2C bus driver architecture, with the data structure Algorithm to represent the algorithm, with the data structure Adapter to represent the different bus controller.

A Client object corresponds to a specific I2C bus device, and a I2C device Driver can support multiple Client. Each adapter corresponds to a specific I2C bus controller. Different I2C bus controllers can use the same algorithm Algorithm. I2c-core is the core of the I2C bus driver architecture, in this module, in addition to the bus device driver provides a unified call interface to access specific bus driver functions for read and write or set operations, but also provides A method of adding various supported bus device drivers and bus drivers to the system, and a method of removing them from the system when they are no longer used. I2c-core bus driver system will be divided into two, independent of each other. It is possible to design an I2C device driver for an I2C-bus device without concern for the type of I2C-bus controller in the system, thus increasing its portability. On the other hand, the design of I2C bus driver can not be considered when it will be used to support what kind of equipment. Because i2c-core provides a unified interface, so also for the design of these two types of drive provides a convenient.

4.development examples

The Linux kernel already provides the basic blocks needed for I2C drivers. I2c-core, i2c-dev and i2c-proc are the https://www.graperain.com/ARM-Embedded-System-On-Module/ Linux SOM required by the bus controller and I2C devices. For MPC8250 processor, the kernel also has MPC8260 algorithm module i2c-algo-8260, it also applies to MPC8250 I2C control interface. These modules in the default condition is not compiled into the kernel, so you need to configure the Linux kernel when these modules selected. In the development of the author needs to achieve is I2C bus controller driver and I2C device EEPROM driver.

4.1 I2C bus controller driver design</p...

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