No Boot Time Difference: First And Subsequent Boots (After Programming Slimbootloader Image)

[Siddhartha]

Hi.

We use Slimbootloader MR8 code (release image) on the i7-1185GRE processor on a custom

circuit board based on UP3 Tiger Lake.

After programming the Slimbootloader image to our circuit board:

1. We power-cycle & observe a certain boot time (say Tfirst_boot).

2. We power-cycle few more times & observe the boot times (say Tsecond_boot, Tthird_boot ...).

We expect: Tfirst_boot should be larger than subsequent boot times since memory training

should NOT be repeated after the first boot. But we don't see such behaviour.

Instead,  Tsecond_boot, Tthird_boot  etc are comparable to Tfirst_boot .

What's going on? What Slimbootloader settings allow memory training only once?

Thanks.

[CarlosAM_INTEL]

Hello, @Siddhartha:

Thank you for contacting Intel Embedded Community.

The information that may help you as a reference is stated in the following website:

https://slimbootloader.github.io/developer-guides/boot-performance.html

Best regards,

@CarlosAM_INTEL.

[Siddhartha]

Hi Carlos.

Thanks for your reply. We have seen that link before, but it doesn't solve our problem.

I forgot to mention in my post:

    The memory init code (FspMemoryInit) seems to lie in the Intel FSP binary provided with Slimbootloader.

We don't know how to configure Slimboot such that memory training occurs just once. What do you suggest?

Thanks.

[CarlosAM_INTEL]

Hello, @Siddhartha:

Thanks for your reply.

We suggest as a reference addressing your questions to the channel stated on the following website:

https://github.com/intel/FSP/issues

Best regards,

@CarlosAM_INTEL.

[Siddhartha]

Thanks  @CarlosAM_INTEL, We have posted on that website. Let's hope they can solve our problem!

[joses_C_Intel]

Hi @CarlosAM_INTEL, team,

Good evening. I'm Josh and I am currently looking into this issue. 

Can someone assist @Siddhartha on how to obtain IPS access? I already made some preliminary investigations, but to move forward, this should be submitted as an IPS ticket which I need to own.

With best regards,

Josh

[CarlosAM_INTEL]

Hello, @joses_C_Intel:

Thank you for contacting Intel Embedded Community.

We sent an email to your address with information that may answer your previous communication.

Best regards,

@CarlosAM_INTEL. 

[joses_C_Intel]

Hi @CarlosAM_INTEL ,

Good morning.  Got it. Thanks a lot!

Hi @Siddhartha ,

Good morning. Please contact your local FAE on IPS access. I will take it from there.

With best regards,

Josh

[Siddhartha]

Hi Josh (@joses_C_Intel).

Thanks for your post. Currently we do NOT have an assigned FAE.

We have contacted an Intel Senior FAE (in Bengaluru, India) today. (In fact, I've sent him a link to this conversation.)

We have asked him to recommend an FAE. Based on his recommendation, we will get back to you.

Thanks for your assistance!

[Siddhartha]

 @CarlosAM_INTEL, @joses_C_Intel

Hi Josh,

I got the ability to make a new IPS case (with the Tigerlake product) only now. Sorry for the delay!

The IPS Case Number is XXXXXXXX.

Hope you can help us now. Thanks!

[CarlosAM_INTEL]

Hello, @Siddhartha:

Thanks for your update, which has been edited to avoid showing confidential information.

We are glad and we suggest stay tuned to the case that you have created in the cited channel. 

Best regards,

@CarlosAM_INTEL.