there is a PCI Express ECN called TLP Hints. Essentially it allows tagging data with a destination ID and a few attributes. One conceivable use would be to send critical data to a particular cache without writing through to memory and following this immediately by an MSI-MSI-X message. The IRP routine would then already find the critical data in the cache when it starts up: i.e. an improvement on Interrupt latency. Assuming the details of right target core, local memory (if NUMA) etc. etc. are set up correctly, of course.
So the real question, do any (preferrably high-end embedded for Xeon / Core ) chip sets currently support this feature. If not, are any scheduled for release in 2012?
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TLP Hints is a feature of PCI Express 2.1. Follow the link below to a paper that provides some additional info on PCIe 2.1 and 3.0:
I am told that the processor platforms currently shipping from Intel are at 2.0 level, not surprising considering the 3.0 spec was only recently published
While I can't make a direction statement on behalf of Intel, I think it's a no brainer that since Intel has spearheaded PCIe innovation ever since the inception of the original PCI that you will see 2.1 / 3.0 support in the processor future roadmap. In fact if you Google "Intel PCI Express 3.0" you will find third-party articles on the subject.
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I hope this helps.
J. Felix McNulty
Community Moderator (Intel contractor)