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Beginner
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SIO_SPI_1 for UART configuration

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Based on Apollo lake SOC which is in MRB board, we want to configure SIO_SPI_1 as one UART port according to the document # 562447 (looks SPI_1 can be set as LPSS_UART3).

however from Intel document # 557555 EDS file: "the SPI functionality of SIO_SPI_1 and SIO_SPI_2 is not POR and these signals can be used as GPIOs ONLY."

Can Intel clarify which one statement is correct ?

thanks.

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For Apollo Lake-I, i.e. Atom E3900/A3900 series, the pins can be used in UART mode, as UART3, if muxed as Fn2. See Table 9 of # 558402. I have raised a ticket for the documentation to be updated, which currently does not mention the Fn2 information.

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Moderator
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Hello, yong_hou :

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please clarify if the cited "MRB Board" has been manufactured by you or a third-party manufacturer? In case that it is from a third-party manufacturer please give us all the information related to it.

By the way, could you please give us the part number and SKU of the processor related to it?

Also, could you please let us know the revision and release date of the cited documents?

Waiting for the information that should answer these questions.

Best regards,

Carlos_A.

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hello Carlos A:

thanks for the reply, MRB board (Gordon Ridge and Modular Reference Boards) is the Intel reference board. Please know the following board information,

Intel Gordon Ridge BMP Versions

- Intel Part # J24248-400,

- PCB:Fab D and above version

- SOC: APL-I ES2 (B1)

- SKU: high

thanks.

Yong

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adding some doc# revision information:

- 562447: Revision 0.5

- 557555: Revision 2.2

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Hello, yong_hou :

Thanks for your updates.

We suggest you use the updated information because it contains corrections that have been found of information stated in the early stages of the platforms.

Due to this fact, the proper information should be the stated in the second note of Table 2.20, on page 40 of the https://cdrdv2.intel.com/v1/dl/getContent/557555 Intel(R) Pentium(R) and Celeron(R) Processor N- and J- Series [Formerly Apollo Lake] External Design Specification [EDS] - Volume 1 of 3, Revision 2.4, May 2017 document # 557555.

It is accessible when you are logged into your Resource & Design Center (RDC) privileged account. It can be requested by filling out the https://www.intel.com/content/www/us/en/forms/design/contact-support.html RDC Account Support form.

We hope that this information may help you.

Best regards,

Carlos_A.

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For Apollo Lake-I, i.e. Atom E3900/A3900 series, the pins can be used in UART mode, as UART3, if muxed as Fn2. See Table 9 of # 558402. I have raised a ticket for the documentation to be updated, which currently does not mention the Fn2 information.

View solution in original post

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@ Ursula

thanks for the confirmation, that clarified my concerns.

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